fe6d9c0825
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
367 lines
13 KiB
C
367 lines
13 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* Based on radeon_winsys.h which is:
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* Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
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* Copyright 2010 Marek Olšák <maraeo@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_RADEON_WINSYS_H
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#define RADV_RADEON_WINSYS_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include "main/macros.h"
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#include "amd_family.h"
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#define FREE(x) free(x)
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enum radeon_bo_domain { /* bitfield */
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RADEON_DOMAIN_GTT = 2,
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RADEON_DOMAIN_VRAM = 4,
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RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
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};
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enum radeon_bo_flag { /* bitfield */
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RADEON_FLAG_GTT_WC = (1 << 0),
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RADEON_FLAG_CPU_ACCESS = (1 << 1),
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RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
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RADEON_FLAG_VIRTUAL = (1 << 3)
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};
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enum radeon_bo_usage { /* bitfield */
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RADEON_USAGE_READ = 2,
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RADEON_USAGE_WRITE = 4,
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RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
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};
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enum ring_type {
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RING_GFX = 0,
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RING_COMPUTE,
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RING_DMA,
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RING_UVD,
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RING_VCE,
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RING_LAST,
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};
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struct radeon_winsys_cs {
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unsigned cdw; /* Number of used dwords. */
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unsigned max_dw; /* Maximum number of dwords. */
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uint32_t *buf; /* The base pointer of the chunk. */
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};
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struct radeon_info {
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/* PCI info: domain:bus:dev:func */
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uint32_t pci_domain;
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uint32_t pci_bus;
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uint32_t pci_dev;
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uint32_t pci_func;
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/* Device info. */
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uint32_t pci_id;
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enum radeon_family family;
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const char *name;
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enum chip_class chip_class;
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uint32_t gart_page_size;
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uint64_t gart_size;
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uint64_t vram_size;
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uint64_t visible_vram_size;
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bool has_dedicated_vram;
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bool has_virtual_memory;
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bool gfx_ib_pad_with_type2;
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bool has_uvd;
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uint32_t sdma_rings;
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uint32_t compute_rings;
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uint32_t vce_fw_version;
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uint32_t vce_harvest_config;
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uint32_t clock_crystal_freq; /* in kHz */
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/* Kernel info. */
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uint32_t drm_major; /* version */
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uint32_t drm_minor;
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uint32_t drm_patchlevel;
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bool has_userptr;
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/* Shader cores. */
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uint32_t r600_max_quad_pipes; /* wave size / 16 */
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uint32_t max_shader_clock;
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uint32_t num_good_compute_units;
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uint32_t max_se; /* shader engines */
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uint32_t max_sh_per_se; /* shader arrays per shader engine */
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/* Render backends (color + depth blocks). */
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uint32_t r300_num_gb_pipes;
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uint32_t r300_num_z_pipes;
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uint32_t r600_gb_backend_map; /* R600 harvest config */
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bool r600_gb_backend_map_valid;
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uint32_t r600_num_banks;
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uint32_t num_render_backends;
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uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
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uint32_t pipe_interleave_bytes;
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uint32_t enabled_rb_mask; /* GCN harvest config */
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/* Tile modes. */
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uint32_t si_tile_mode_array[32];
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uint32_t cik_macrotile_mode_array[16];
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};
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#define RADEON_SURF_MAX_LEVEL 32
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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#define RADEON_SURF_TYPE_2D 1
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#define RADEON_SURF_TYPE_3D 2
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#define RADEON_SURF_TYPE_CUBEMAP 3
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#define RADEON_SURF_TYPE_1D_ARRAY 4
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
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#define RADEON_SURF_MODE_1D 2
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#define RADEON_SURF_MODE_2D 3
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
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#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
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#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
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#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
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#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
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struct radeon_surf_info {
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uint32_t width;
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uint32_t height;
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uint32_t depth;
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uint32_t samples;
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uint32_t array_size;
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uint32_t levels;
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};
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struct radeon_surf_level {
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uint64_t offset;
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uint64_t slice_size;
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uint32_t nblk_x;
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uint32_t nblk_y;
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uint32_t nblk_z;
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uint32_t pitch_bytes;
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uint32_t mode;
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uint64_t dcc_offset;
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uint64_t dcc_fast_clear_size;
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bool dcc_enabled;
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};
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/* surface defintions from the winsys */
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struct radeon_surf {
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/* These are inputs to the calculator. */
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uint32_t blk_w;
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uint32_t blk_h;
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uint32_t bpe;
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uint32_t flags;
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/* These are return values. Some of them can be set by the caller, but
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* they will be treated as hints (e.g. bankw, bankh) and might be
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* changed by the calculator.
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*/
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uint64_t bo_size;
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uint64_t bo_alignment;
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/* This applies to EG and later. */
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uint32_t bankw;
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uint32_t bankh;
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uint32_t mtilea;
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uint32_t tile_split;
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uint32_t stencil_tile_split;
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uint64_t stencil_offset;
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struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
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struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
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uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
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uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
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uint32_t pipe_config;
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uint32_t num_banks;
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uint32_t macro_tile_index;
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uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */
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/* Whether the depth miptree or stencil miptree as used by the DB are
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* adjusted from their TC compatible form to ensure depth/stencil
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* compatibility. If either is true, the corresponding plane cannot be
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* sampled from.
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*/
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bool depth_adjusted;
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bool stencil_adjusted;
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uint64_t dcc_size;
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uint64_t dcc_alignment;
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uint64_t htile_size;
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uint64_t htile_slice_size;
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uint64_t htile_alignment;
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};
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enum radeon_bo_layout {
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RADEON_LAYOUT_LINEAR = 0,
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RADEON_LAYOUT_TILED,
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RADEON_LAYOUT_SQUARETILED,
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RADEON_LAYOUT_UNKNOWN
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};
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/* Tiling info for display code, DRI sharing, and other data. */
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struct radeon_bo_metadata {
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/* Tiling flags describing the texture layout for display code
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* and DRI sharing.
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*/
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enum radeon_bo_layout microtile;
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enum radeon_bo_layout macrotile;
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unsigned pipe_config;
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unsigned bankw;
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unsigned bankh;
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unsigned tile_split;
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unsigned mtilea;
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unsigned num_banks;
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unsigned stride;
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bool scanout;
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/* Additional metadata associated with the buffer, in bytes.
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* The maximum size is 64 * 4. This is opaque for the winsys & kernel.
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* Supported by amdgpu only.
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*/
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uint32_t size_metadata;
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uint32_t metadata[64];
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};
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struct radeon_winsys_bo;
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struct radeon_winsys_fence;
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struct radeon_winsys_sem;
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struct radeon_winsys {
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void (*destroy)(struct radeon_winsys *ws);
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void (*query_info)(struct radeon_winsys *ws,
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struct radeon_info *info);
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struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
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uint64_t size,
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unsigned alignment,
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enum radeon_bo_domain domain,
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enum radeon_bo_flag flags);
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void (*buffer_destroy)(struct radeon_winsys_bo *bo);
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void *(*buffer_map)(struct radeon_winsys_bo *bo);
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struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
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int fd,
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unsigned *stride, unsigned *offset);
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bool (*buffer_get_fd)(struct radeon_winsys *ws,
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struct radeon_winsys_bo *bo,
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int *fd);
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void (*buffer_unmap)(struct radeon_winsys_bo *bo);
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uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
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void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
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struct radeon_bo_metadata *md);
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void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
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uint64_t offset, uint64_t size,
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struct radeon_winsys_bo *bo, uint64_t bo_offset);
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struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
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void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
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bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
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enum ring_type ring_type, int ring_index);
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struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
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enum ring_type ring_type);
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void (*cs_destroy)(struct radeon_winsys_cs *cs);
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void (*cs_reset)(struct radeon_winsys_cs *cs);
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bool (*cs_finalize)(struct radeon_winsys_cs *cs);
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void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
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int (*cs_submit)(struct radeon_winsys_ctx *ctx,
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int queue_index,
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struct radeon_winsys_cs **cs_array,
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unsigned cs_count,
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struct radeon_winsys_cs *initial_preamble_cs,
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struct radeon_winsys_cs *continue_preamble_cs,
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struct radeon_winsys_sem **wait_sem,
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unsigned wait_sem_count,
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struct radeon_winsys_sem **signal_sem,
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unsigned signal_sem_count,
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bool can_patch,
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struct radeon_winsys_fence *fence);
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void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
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struct radeon_winsys_bo *bo,
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uint8_t priority);
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void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
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struct radeon_winsys_cs *child);
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void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
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int (*surface_init)(struct radeon_winsys *ws,
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const struct radeon_surf_info *surf_info,
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struct radeon_surf *surf);
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int (*surface_best)(struct radeon_winsys *ws,
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struct radeon_surf *surf);
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struct radeon_winsys_fence *(*create_fence)();
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void (*destroy_fence)(struct radeon_winsys_fence *fence);
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bool (*fence_wait)(struct radeon_winsys *ws,
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struct radeon_winsys_fence *fence,
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bool absolute,
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uint64_t timeout);
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struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
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void (*destroy_sem)(struct radeon_winsys_sem *sem);
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};
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static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
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{
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cs->buf[cs->cdw++] = value;
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}
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static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
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const uint32_t *values, unsigned count)
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{
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memcpy(cs->buf + cs->cdw, values, count * 4);
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cs->cdw += count;
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}
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#endif /* RADV_RADEON_WINSYS_H */
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