fc9f502a5b
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Cc: 20.2 <mesa-stable> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6212>
627 lines
22 KiB
Python
627 lines
22 KiB
Python
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template = """\
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/*
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* Copyright (c) 2019 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* This file was generated by aco_builder_h.py
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*/
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#ifndef _ACO_BUILDER_
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#define _ACO_BUILDER_
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#include "aco_ir.h"
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#include "util/u_math.h"
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#include "util/bitscan.h"
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namespace aco {
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enum dpp_ctrl {
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_dpp_quad_perm = 0x000,
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_dpp_row_sl = 0x100,
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_dpp_row_sr = 0x110,
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_dpp_row_rr = 0x120,
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dpp_wf_sl1 = 0x130,
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dpp_wf_rl1 = 0x134,
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dpp_wf_sr1 = 0x138,
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dpp_wf_rr1 = 0x13C,
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dpp_row_mirror = 0x140,
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dpp_row_half_mirror = 0x141,
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dpp_row_bcast15 = 0x142,
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dpp_row_bcast31 = 0x143
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};
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inline dpp_ctrl
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dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
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{
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assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
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return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
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}
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inline dpp_ctrl
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dpp_row_sl(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
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}
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inline dpp_ctrl
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dpp_row_sr(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
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}
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inline dpp_ctrl
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dpp_row_rr(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount);
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}
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inline unsigned
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ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
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{
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assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
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return and_mask | (or_mask << 5) | (xor_mask << 10);
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}
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aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
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extern uint8_t int8_mul_table[512];
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enum sendmsg {
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sendmsg_none = 0,
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_sendmsg_gs = 2,
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_sendmsg_gs_done = 3,
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sendmsg_save_wave = 4,
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sendmsg_stall_wave_gen = 5,
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sendmsg_halt_waves = 6,
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sendmsg_ordered_ps_done = 7,
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sendmsg_early_prim_dealloc = 8,
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sendmsg_gs_alloc_req = 9,
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sendmsg_id_mask = 0xf,
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};
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inline sendmsg
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sendmsg_gs(bool cut, bool emit, unsigned stream)
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{
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assert(stream < 4);
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return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8));
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}
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inline sendmsg
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sendmsg_gs_done(bool cut, bool emit, unsigned stream)
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{
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assert(stream < 4);
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return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8));
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}
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class Builder {
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public:
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struct Result {
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Instruction *instr;
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Result(Instruction *instr) : instr(instr) {}
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operator Instruction *() const {
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return instr;
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}
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operator Temp() const {
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return instr->definitions[0].getTemp();
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}
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operator Operand() const {
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return Operand((Temp)*this);
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}
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Definition& def(unsigned index) const {
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return instr->definitions[index];
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}
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aco_ptr<Instruction> get_ptr() const {
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return aco_ptr<Instruction>(instr);
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}
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};
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struct Op {
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Operand op;
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Op(Temp tmp) : op(tmp) {}
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Op(Operand op_) : op(op_) {}
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Op(Result res) : op((Temp)res) {}
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};
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enum WaveSpecificOpcode {
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s_cselect = (unsigned) aco_opcode::s_cselect_b64,
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s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
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s_and = (unsigned) aco_opcode::s_and_b64,
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s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
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s_or = (unsigned) aco_opcode::s_or_b64,
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s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
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s_not = (unsigned) aco_opcode::s_not_b64,
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s_mov = (unsigned) aco_opcode::s_mov_b64,
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s_wqm = (unsigned) aco_opcode::s_wqm_b64,
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s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
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s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
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s_xnor = (unsigned) aco_opcode::s_xnor_b64,
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s_xor = (unsigned) aco_opcode::s_xor_b64,
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s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
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s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
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s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
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};
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Program *program;
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bool use_iterator;
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bool start; // only when use_iterator == false
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RegClass lm;
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std::vector<aco_ptr<Instruction>> *instructions;
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std::vector<aco_ptr<Instruction>>::iterator it;
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bool is_precise = false;
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bool is_nuw = false;
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Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(NULL) {}
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Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
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Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
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Builder precise() const {
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Builder res = *this;
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res.is_precise = true;
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return res;
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};
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Builder nuw() const {
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Builder res = *this;
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res.is_nuw = true;
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return res;
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}
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void moveEnd(Block *block) {
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instructions = &block->instructions;
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}
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void reset() {
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use_iterator = false;
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start = false;
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instructions = NULL;
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}
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void reset(Block *block) {
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use_iterator = false;
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start = false;
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instructions = &block->instructions;
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}
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void reset(std::vector<aco_ptr<Instruction>> *instrs) {
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use_iterator = false;
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start = false;
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instructions = instrs;
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}
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void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
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use_iterator = true;
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start = false;
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instructions = instrs;
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it = instr_it;
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}
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Result insert(aco_ptr<Instruction> instr) {
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Instruction *instr_ptr = instr.get();
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if (instructions) {
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if (use_iterator) {
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it = instructions->emplace(it, std::move(instr));
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it = std::next(it);
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} else if (!start) {
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instructions->emplace_back(std::move(instr));
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} else {
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instructions->emplace(instructions->begin(), std::move(instr));
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}
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}
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return Result(instr_ptr);
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}
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Result insert(Instruction* instr) {
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if (instructions) {
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if (use_iterator) {
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it = instructions->emplace(it, aco_ptr<Instruction>(instr));
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it = std::next(it);
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} else if (!start) {
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instructions->emplace_back(aco_ptr<Instruction>(instr));
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} else {
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instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
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}
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}
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return Result(instr);
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}
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Temp tmp(RegClass rc) {
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return (Temp){program->allocateId(), rc};
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}
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Temp tmp(RegType type, unsigned size) {
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return (Temp){program->allocateId(), RegClass(type, size)};
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}
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Definition def(RegClass rc) {
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return Definition((Temp){program->allocateId(), rc});
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}
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Definition def(RegType type, unsigned size) {
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return Definition((Temp){program->allocateId(), RegClass(type, size)});
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}
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Definition def(RegClass rc, PhysReg reg) {
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return Definition(program->allocateId(), reg, rc);
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}
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inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
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if (program->wave_size == 64)
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return (aco_opcode) opcode;
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switch (opcode) {
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case s_cselect:
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return aco_opcode::s_cselect_b32;
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case s_cmp_lg:
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return aco_opcode::s_cmp_lg_u32;
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case s_and:
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return aco_opcode::s_and_b32;
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case s_andn2:
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return aco_opcode::s_andn2_b32;
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case s_or:
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return aco_opcode::s_or_b32;
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case s_orn2:
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return aco_opcode::s_orn2_b32;
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case s_not:
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return aco_opcode::s_not_b32;
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case s_mov:
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return aco_opcode::s_mov_b32;
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case s_wqm:
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return aco_opcode::s_wqm_b32;
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case s_and_saveexec:
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return aco_opcode::s_and_saveexec_b32;
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case s_or_saveexec:
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return aco_opcode::s_or_saveexec_b32;
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case s_xnor:
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return aco_opcode::s_xnor_b32;
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case s_xor:
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return aco_opcode::s_xor_b32;
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case s_bcnt1_i32:
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return aco_opcode::s_bcnt1_i32_b32;
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case s_bitcmp1:
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return aco_opcode::s_bitcmp1_b32;
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case s_ff1_i32:
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return aco_opcode::s_ff1_i32_b32;
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default:
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unreachable("Unsupported wave specific opcode.");
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}
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}
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% for fixed in ['m0', 'vcc', 'exec', 'scc']:
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Operand ${fixed}(Temp tmp) {
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% if fixed == 'vcc' or fixed == 'exec':
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//vcc_hi and exec_hi can still be used in wave32
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assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8);
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% endif
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Operand op(tmp);
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op.setFixed(aco::${fixed});
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return op;
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}
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Definition ${fixed}(Definition def) {
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% if fixed == 'vcc' or fixed == 'exec':
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//vcc_hi and exec_hi can still be used in wave32
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assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
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% endif
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def.setFixed(aco::${fixed});
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return def;
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}
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Definition hint_${fixed}(Definition def) {
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% if fixed == 'vcc' or fixed == 'exec':
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//vcc_hi and exec_hi can still be used in wave32
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assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
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% endif
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def.setHint(aco::${fixed});
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return def;
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}
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% endfor
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/* hand-written helpers */
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Temp as_uniform(Op op)
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{
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assert(op.op.isTemp());
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if (op.op.getTemp().type() == RegType::vgpr)
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return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
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else
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return op.op.getTemp();
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}
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Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
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{
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assert(tmp.type() == RegType::vgpr);
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if (imm == 0) {
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return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
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} else if (imm == 1) {
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return copy(dst, Operand(tmp));
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} else if (util_is_power_of_two_or_zero(imm)) {
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return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
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} else if (bits24) {
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return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
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} else {
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Temp imm_tmp = copy(def(v1), Operand(imm));
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return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
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}
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}
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Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
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{
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return v_mul_imm(dst, tmp, imm, true);
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}
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Result copy(Definition dst, Op op_) {
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Operand op = op_.op;
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assert(op.bytes() == dst.bytes());
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if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
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uint32_t imm = op.constantValue();
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if (imm == 0x3e22f983) {
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if (program->chip_class >= GFX8)
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op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */
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} else if (imm >= 0xffff8000 || imm <= 0x7fff) {
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return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
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} else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
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uint32_t rev = util_bitreverse(imm);
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return dst.regClass() == v1 ?
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vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
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sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
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} else if (imm != 0) {
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unsigned start = (ffs(imm) - 1) & 0x1f;
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unsigned size = util_bitcount(imm) & 0x1f;
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if ((((1u << size) - 1u) << start) == imm)
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return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
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}
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}
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if (dst.regClass() == s1) {
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return sop1(aco_opcode::s_mov_b32, dst, op);
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} else if (dst.regClass() == s2) {
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return sop1(aco_opcode::s_mov_b64, dst, op);
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} else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
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return vop1(aco_opcode::v_mov_b32, dst, op);
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} else if (op.bytes() > 2) {
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return pseudo(aco_opcode::p_create_vector, dst, op);
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} else if (op.bytes() == 1 && op.isConstant()) {
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uint8_t val = op.constantValue();
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Operand op32((uint32_t)val | (val & 0x80u ? 0xffffff00u : 0u));
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aco_ptr<SDWA_instruction> sdwa;
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if (op32.isLiteral()) {
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sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mul_u32_u24, asSDWA(Format::VOP2), 2, 1));
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uint32_t a = (uint32_t)int8_mul_table[val * 2];
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uint32_t b = (uint32_t)int8_mul_table[val * 2 + 1];
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sdwa->operands[0] = Operand(a | (a & 0x80u ? 0xffffff00u : 0x0u));
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sdwa->operands[1] = Operand(b | (b & 0x80u ? 0xffffff00u : 0x0u));
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} else {
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sdwa.reset(create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1));
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sdwa->operands[0] = op32;
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}
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sdwa->definitions[0] = dst;
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sdwa->sel[0] = sdwa_udword;
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sdwa->sel[1] = sdwa_udword;
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sdwa->dst_sel = sdwa_ubyte;
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sdwa->dst_preserve = true;
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return insert(std::move(sdwa));
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} else if (op.bytes() == 2 && op.isConstant() && !op.isLiteral()) {
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aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_add_f16, asSDWA(Format::VOP2), 2, 1)};
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sdwa->operands[0] = op;
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sdwa->operands[1] = Operand(0u);
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sdwa->definitions[0] = dst;
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sdwa->sel[0] = sdwa_uword;
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sdwa->sel[1] = sdwa_udword;
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sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
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sdwa->dst_preserve = true;
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return insert(std::move(sdwa));
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} else if (dst.regClass().is_subdword()) {
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if (program->chip_class >= GFX8) {
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aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
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sdwa->operands[0] = op;
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sdwa->definitions[0] = dst;
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sdwa->sel[0] = op.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
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sdwa->dst_sel = dst.bytes() == 1 ? sdwa_ubyte : sdwa_uword;
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sdwa->dst_preserve = true;
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return insert(std::move(sdwa));
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} else {
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return vop1(aco_opcode::v_mov_b32, dst, op);
|
|
}
|
|
} else {
|
|
unreachable("Unhandled case in bld.copy()");
|
|
}
|
|
}
|
|
|
|
Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
|
|
if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
|
|
std::swap(a, b);
|
|
assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
|
|
|
|
if (!carry_in.op.isUndefined())
|
|
return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
|
|
else if (program->chip_class >= GFX10 && carry_out)
|
|
return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b);
|
|
else if (program->chip_class < GFX9 || carry_out)
|
|
return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
|
|
else
|
|
return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
|
|
}
|
|
|
|
Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
|
|
{
|
|
if (!borrow.op.isUndefined() || program->chip_class < GFX9)
|
|
carry_out = true;
|
|
|
|
bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
|
|
if (reverse)
|
|
std::swap(a, b);
|
|
assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
|
|
|
|
aco_opcode op;
|
|
Temp carry;
|
|
if (carry_out) {
|
|
carry = tmp(s2);
|
|
if (borrow.op.isUndefined())
|
|
op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
|
|
else
|
|
op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
|
|
} else {
|
|
op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
|
|
}
|
|
bool vop3 = false;
|
|
if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
|
|
vop3 = true;
|
|
op = aco_opcode::v_subrev_co_u32_e64;
|
|
} else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
|
|
vop3 = true;
|
|
op = aco_opcode::v_sub_co_u32_e64;
|
|
}
|
|
|
|
int num_ops = borrow.op.isUndefined() ? 2 : 3;
|
|
int num_defs = carry_out ? 2 : 1;
|
|
aco_ptr<Instruction> sub;
|
|
if (vop3)
|
|
sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
|
|
else
|
|
sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
|
|
sub->operands[0] = a.op;
|
|
sub->operands[1] = b.op;
|
|
if (!borrow.op.isUndefined())
|
|
sub->operands[2] = borrow.op;
|
|
sub->definitions[0] = dst;
|
|
if (carry_out) {
|
|
sub->definitions[1] = Definition(carry);
|
|
sub->definitions[1].setHint(aco::vcc);
|
|
}
|
|
return insert(std::move(sub));
|
|
}
|
|
|
|
Result readlane(Definition dst, Op vsrc, Op lane)
|
|
{
|
|
if (program->chip_class >= GFX8)
|
|
return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
|
|
else
|
|
return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
|
|
}
|
|
Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
|
|
if (program->chip_class >= GFX8)
|
|
return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
|
|
else
|
|
return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
|
|
}
|
|
<%
|
|
import itertools
|
|
formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
|
|
("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
|
|
("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
|
|
("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
|
|
("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
|
|
("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
|
|
("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
|
|
("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
|
|
("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
|
|
("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]),
|
|
("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 3), (1, 3)]),
|
|
("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
|
|
("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
|
|
("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
|
|
("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]),
|
|
("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
|
|
("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
|
|
("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])),
|
|
("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
|
|
("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
|
|
("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
|
|
("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
|
|
("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
|
|
("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
|
|
("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
|
|
("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
|
|
("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
|
|
("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
|
|
("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
|
|
formats = [(f if len(f) == 5 else f + ('',)) for f in formats]
|
|
%>\\
|
|
% for name, formats, struct, shapes, extra_field_setup in formats:
|
|
% for num_definitions, num_operands in shapes:
|
|
<%
|
|
args = ['aco_opcode opcode']
|
|
for i in range(num_definitions):
|
|
args.append('Definition def%d' % i)
|
|
for i in range(num_operands):
|
|
args.append('Op op%d' % i)
|
|
for f in formats:
|
|
args += f.get_builder_field_decls()
|
|
%>\\
|
|
|
|
Result ${name}(${', '.join(args)})
|
|
{
|
|
${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
|
|
% for i in range(num_definitions):
|
|
instr->definitions[${i}] = def${i};
|
|
instr->definitions[${i}].setPrecise(is_precise);
|
|
instr->definitions[${i}].setNUW(is_nuw);
|
|
% endfor
|
|
% for i in range(num_operands):
|
|
instr->operands[${i}] = op${i}.op;
|
|
% endfor
|
|
% for f in formats:
|
|
% for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
|
|
instr->${dest} = ${field_name};
|
|
% endfor
|
|
${f.get_builder_initialization(num_operands)}
|
|
% endfor
|
|
${extra_field_setup}
|
|
return insert(instr);
|
|
}
|
|
|
|
% if name == 'sop1' or name == 'sop2' or name == 'sopc':
|
|
<%
|
|
args[0] = 'WaveSpecificOpcode opcode'
|
|
params = []
|
|
for i in range(num_definitions):
|
|
params.append('def%d' % i)
|
|
for i in range(num_operands):
|
|
params.append('op%d' % i)
|
|
%>\\
|
|
|
|
inline Result ${name}(${', '.join(args)})
|
|
{
|
|
return ${name}(w64or32(opcode), ${', '.join(params)});
|
|
}
|
|
|
|
% endif
|
|
% endfor
|
|
% endfor
|
|
};
|
|
|
|
}
|
|
#endif /* _ACO_BUILDER_ */"""
|
|
|
|
from aco_opcodes import opcodes, Format
|
|
from mako.template import Template
|
|
|
|
print(Template(template).render(opcodes=opcodes, Format=Format))
|