fab56a0d03b8e1470a1fabf78499d86a58e0319a

The initial logic was to remember the place were SPI_SHADER_PGM_LO_* are written, then assume that we can get the register offset because the sequence would always be: PKT3_SET_SH_REG SPI_SHADER_PGM_LO_* register offset VA low 32 bits value <- reg_va_low_idx The problem is that this sequence isn't guaranteed, for instance we can get this instead: 0 c0067600 | 1 00000046 | 2 003ffffd | SPI_SHADER_PGM_RSRC3_VS 3 00000020 | SPI_SHADER_LATE_ALLOC_VS 4 * 00002080 | SPI_SHADER_PGM_LO_VS 5 00000080 | SPI_SHADER_PGM_HI_VS So the assert in si_state_draw.cpp would fail as well as the VA update logic. So instead remember which the SPI_SHADER_PGM_LO_* offset, and the low 32 bits of the VA in si_update_shaders. Fixes:8034a71430
("radeonsi/sqtt: re-export shaders in a single bo") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26774> (cherry picked from commitb55a2065e0
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