111881abac
V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec()
gen10_init_atoms() (Jason)
Remove Vulkan changes. Do them later in a separate patch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
722 lines
22 KiB
C
722 lines
22 KiB
C
/*
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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*/
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#include "brw_eu_defines.h"
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#include "brw_eu.h"
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#include "brw_shader.h"
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#include "common/gen_debug.h"
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#include "util/ralloc.h"
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/**
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* Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
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*
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* This is different than reg_encoding from brw_disasm.c in that it operates
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* on the abstract enum values, rather than the generation-specific encoding.
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*/
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const char *
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brw_reg_type_letters(unsigned type)
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{
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const char *names[] = {
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[BRW_REGISTER_TYPE_UD] = "UD",
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[BRW_REGISTER_TYPE_D] = "D",
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[BRW_REGISTER_TYPE_UW] = "UW",
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[BRW_REGISTER_TYPE_W] = "W",
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[BRW_REGISTER_TYPE_F] = "F",
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[BRW_REGISTER_TYPE_UB] = "UB",
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[BRW_REGISTER_TYPE_B] = "B",
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[BRW_REGISTER_TYPE_UV] = "UV",
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[BRW_REGISTER_TYPE_V] = "V",
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[BRW_REGISTER_TYPE_VF] = "VF",
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[BRW_REGISTER_TYPE_DF] = "DF",
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[BRW_REGISTER_TYPE_HF] = "HF",
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[BRW_REGISTER_TYPE_UQ] = "UQ",
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[BRW_REGISTER_TYPE_Q] = "Q",
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};
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assert(type <= BRW_REGISTER_TYPE_Q);
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return names[type];
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}
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/* Returns a conditional modifier that negates the condition. */
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enum brw_conditional_mod
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brw_negate_cmod(uint32_t cmod)
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{
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switch (cmod) {
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case BRW_CONDITIONAL_Z:
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return BRW_CONDITIONAL_NZ;
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case BRW_CONDITIONAL_NZ:
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return BRW_CONDITIONAL_Z;
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case BRW_CONDITIONAL_G:
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return BRW_CONDITIONAL_LE;
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case BRW_CONDITIONAL_GE:
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return BRW_CONDITIONAL_L;
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case BRW_CONDITIONAL_L:
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return BRW_CONDITIONAL_GE;
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case BRW_CONDITIONAL_LE:
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return BRW_CONDITIONAL_G;
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default:
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return ~0;
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}
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}
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/* Returns the corresponding conditional mod for swapping src0 and
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* src1 in e.g. CMP.
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*/
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enum brw_conditional_mod
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brw_swap_cmod(uint32_t cmod)
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{
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switch (cmod) {
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case BRW_CONDITIONAL_Z:
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case BRW_CONDITIONAL_NZ:
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return cmod;
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case BRW_CONDITIONAL_G:
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return BRW_CONDITIONAL_L;
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case BRW_CONDITIONAL_GE:
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return BRW_CONDITIONAL_LE;
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case BRW_CONDITIONAL_L:
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return BRW_CONDITIONAL_G;
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case BRW_CONDITIONAL_LE:
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return BRW_CONDITIONAL_GE;
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default:
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return BRW_CONDITIONAL_NONE;
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}
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}
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/**
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* Get the least significant bit offset of the i+1-th component of immediate
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* type \p type. For \p i equal to the two's complement of j, return the
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* offset of the j-th component starting from the end of the vector. For
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* scalar register types return zero.
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*/
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static unsigned
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imm_shift(enum brw_reg_type type, unsigned i)
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{
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assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
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"Not implemented.");
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if (type == BRW_REGISTER_TYPE_VF)
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return 8 * (i & 3);
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else
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return 0;
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}
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/**
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* Swizzle an arbitrary immediate \p x of the given type according to the
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* permutation specified as \p swz.
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*/
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uint32_t
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brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
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{
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if (imm_shift(type, 1)) {
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const unsigned n = 32 / imm_shift(type, 1);
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uint32_t y = 0;
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for (unsigned i = 0; i < n; i++) {
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/* Shift the specified component all the way to the right and left to
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* discard any undesired L/MSBs, then shift it right into component i.
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*/
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y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
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<< imm_shift(type, ~0u)
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>> imm_shift(type, ~0u - i);
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}
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return y;
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} else {
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return x;
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}
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}
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void
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brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
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{
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brw_inst_set_exec_size(p->devinfo, p->current, value);
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}
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void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
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{
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brw_inst_set_pred_control(p->devinfo, p->current, pc);
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}
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void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
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{
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brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
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}
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void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
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{
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if (p->devinfo->gen >= 7)
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brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
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brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
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}
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void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
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{
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brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
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}
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void
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brw_set_default_compression_control(struct brw_codegen *p,
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enum brw_compression compression_control)
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{
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if (p->devinfo->gen >= 6) {
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/* Since we don't use the SIMD32 support in gen6, we translate
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* the pre-gen6 compression control here.
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*/
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switch (compression_control) {
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case BRW_COMPRESSION_NONE:
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/* This is the "use the first set of bits of dmask/vmask/arf
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* according to execsize" option.
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*/
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brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
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break;
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case BRW_COMPRESSION_2NDHALF:
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/* For SIMD8, this is "use the second set of 8 bits." */
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brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
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break;
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case BRW_COMPRESSION_COMPRESSED:
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/* For SIMD16 instruction compression, use the first set of 16 bits
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* since we don't do SIMD32 dispatch.
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*/
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brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
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break;
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default:
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unreachable("not reached");
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}
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} else {
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brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
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}
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}
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/**
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* Enable or disable instruction compression on the given instruction leaving
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* the currently selected channel enable group untouched.
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*/
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void
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brw_inst_set_compression(const struct gen_device_info *devinfo,
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brw_inst *inst, bool on)
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{
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if (devinfo->gen >= 6) {
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/* No-op, the EU will figure out for us whether the instruction needs to
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* be compressed.
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*/
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} else {
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/* The channel group and compression controls are non-orthogonal, there
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* are two possible representations for uncompressed instructions and we
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* may need to preserve the current one to avoid changing the selected
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* channel group inadvertently.
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*/
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if (on)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
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else if (brw_inst_qtr_control(devinfo, inst)
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== BRW_COMPRESSION_COMPRESSED)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
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}
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}
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void
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brw_set_default_compression(struct brw_codegen *p, bool on)
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{
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brw_inst_set_compression(p->devinfo, p->current, on);
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}
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/**
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* Apply the range of channel enable signals given by
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* [group, group + exec_size) to the instruction passed as argument.
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*/
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void
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brw_inst_set_group(const struct gen_device_info *devinfo,
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brw_inst *inst, unsigned group)
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{
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if (devinfo->gen >= 7) {
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assert(group % 4 == 0 && group < 32);
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brw_inst_set_qtr_control(devinfo, inst, group / 8);
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brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
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} else if (devinfo->gen == 6) {
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assert(group % 8 == 0 && group < 32);
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brw_inst_set_qtr_control(devinfo, inst, group / 8);
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} else {
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assert(group % 8 == 0 && group < 16);
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/* The channel group and compression controls are non-orthogonal, there
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* are two possible representations for group zero and we may need to
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* preserve the current one to avoid changing the selected compression
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* enable inadvertently.
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*/
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if (group == 8)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
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else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
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brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
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}
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}
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void
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brw_set_default_group(struct brw_codegen *p, unsigned group)
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{
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brw_inst_set_group(p->devinfo, p->current, group);
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}
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void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
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{
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brw_inst_set_mask_control(p->devinfo, p->current, value);
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}
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void brw_set_default_saturate( struct brw_codegen *p, bool enable )
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{
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brw_inst_set_saturate(p->devinfo, p->current, enable);
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}
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void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
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{
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if (p->devinfo->gen >= 6)
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brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
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}
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void brw_push_insn_state( struct brw_codegen *p )
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{
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assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
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memcpy(p->current + 1, p->current, sizeof(brw_inst));
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p->current++;
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}
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void brw_pop_insn_state( struct brw_codegen *p )
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{
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assert(p->current != p->stack);
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p->current--;
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}
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/***********************************************************************
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*/
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void
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brw_init_codegen(const struct gen_device_info *devinfo,
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struct brw_codegen *p, void *mem_ctx)
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{
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memset(p, 0, sizeof(*p));
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p->devinfo = devinfo;
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/*
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* Set the initial instruction store array size to 1024, if found that
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* isn't enough, then it will double the store size at brw_next_insn()
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* until out of memory.
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*/
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p->store_size = 1024;
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p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
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p->nr_insn = 0;
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p->current = p->stack;
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memset(p->current, 0, sizeof(p->current[0]));
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p->mem_ctx = mem_ctx;
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/* Some defaults?
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*/
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brw_set_default_exec_size(p, BRW_EXECUTE_8);
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brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
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brw_set_default_saturate(p, 0);
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brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
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/* Set up control flow stack */
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p->if_stack_depth = 0;
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p->if_stack_array_size = 16;
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p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
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p->loop_stack_depth = 0;
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p->loop_stack_array_size = 16;
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p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
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p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
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}
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const unsigned *brw_get_program( struct brw_codegen *p,
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unsigned *sz )
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{
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*sz = p->next_insn_offset;
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return (const unsigned *)p->store;
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}
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void
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brw_disassemble(const struct gen_device_info *devinfo,
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const void *assembly, int start, int end, FILE *out)
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{
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bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
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for (int offset = start; offset < end;) {
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const brw_inst *insn = assembly + offset;
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brw_inst uncompacted;
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bool compacted = brw_inst_cmpt_control(devinfo, insn);
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if (0)
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fprintf(out, "0x%08x: ", offset);
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if (compacted) {
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brw_compact_inst *compacted = (void *)insn;
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if (dump_hex) {
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fprintf(out, "0x%08x 0x%08x ",
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((uint32_t *)insn)[1],
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((uint32_t *)insn)[0]);
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}
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brw_uncompact_instruction(devinfo, &uncompacted, compacted);
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insn = &uncompacted;
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offset += 8;
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} else {
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if (dump_hex) {
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fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
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((uint32_t *)insn)[3],
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((uint32_t *)insn)[2],
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((uint32_t *)insn)[1],
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((uint32_t *)insn)[0]);
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}
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offset += 16;
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}
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brw_disassemble_inst(out, devinfo, insn, compacted);
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}
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}
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enum gen {
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GEN4 = (1 << 0),
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GEN45 = (1 << 1),
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GEN5 = (1 << 2),
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GEN6 = (1 << 3),
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GEN7 = (1 << 4),
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GEN75 = (1 << 5),
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GEN8 = (1 << 6),
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GEN9 = (1 << 7),
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GEN10 = (1 << 8),
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GEN_ALL = ~0
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};
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#define GEN_LT(gen) ((gen) - 1)
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#define GEN_GE(gen) (~GEN_LT(gen))
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#define GEN_LE(gen) (GEN_LT(gen) | (gen))
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static const struct opcode_desc opcode_10_descs[] = {
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{ .name = "dim", .nsrc = 1, .ndst = 1, .gens = GEN75 },
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{ .name = "smov", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
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};
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static const struct opcode_desc opcode_35_descs[] = {
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{ .name = "iff", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
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{ .name = "brc", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
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};
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static const struct opcode_desc opcode_38_descs[] = {
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{ .name = "do", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
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{ .name = "case", .nsrc = 0, .ndst = 0, .gens = GEN6 },
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};
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static const struct opcode_desc opcode_44_descs[] = {
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{ .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
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{ .name = "call", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
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};
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static const struct opcode_desc opcode_45_descs[] = {
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{ .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
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{ .name = "ret", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
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};
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static const struct opcode_desc opcode_46_descs[] = {
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{ .name = "push", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
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{ .name = "fork", .nsrc = 0, .ndst = 0, .gens = GEN6 },
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{ .name = "goto", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
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};
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static const struct opcode_desc opcode_descs[128] = {
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[BRW_OPCODE_ILLEGAL] = {
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.name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
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},
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[BRW_OPCODE_MOV] = {
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.name = "mov", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
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},
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[BRW_OPCODE_SEL] = {
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.name = "sel", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
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},
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[BRW_OPCODE_MOVI] = {
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.name = "movi", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
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|
},
|
|
[BRW_OPCODE_NOT] = {
|
|
.name = "not", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_AND] = {
|
|
.name = "and", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_OR] = {
|
|
.name = "or", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_XOR] = {
|
|
.name = "xor", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SHR] = {
|
|
.name = "shr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SHL] = {
|
|
.name = "shl", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[10] = {
|
|
.table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
|
|
},
|
|
/* Reserved - 11 */
|
|
[BRW_OPCODE_ASR] = {
|
|
.name = "asr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
/* Reserved - 13-15 */
|
|
[BRW_OPCODE_CMP] = {
|
|
.name = "cmp", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_CMPN] = {
|
|
.name = "cmpn", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_CSEL] = {
|
|
.name = "csel", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
|
|
},
|
|
[BRW_OPCODE_F32TO16] = {
|
|
.name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
|
|
},
|
|
[BRW_OPCODE_F16TO32] = {
|
|
.name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
|
|
},
|
|
/* Reserved - 21-22 */
|
|
[BRW_OPCODE_BFREV] = {
|
|
.name = "bfrev", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_BFE] = {
|
|
.name = "bfe", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_BFI1] = {
|
|
.name = "bfi1", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_BFI2] = {
|
|
.name = "bfi2", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
/* Reserved - 27-31 */
|
|
[BRW_OPCODE_JMPI] = {
|
|
.name = "jmpi", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[33] = {
|
|
.name = "brd", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_IF] = {
|
|
.name = "if", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[35] = {
|
|
.table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
|
|
},
|
|
[BRW_OPCODE_ELSE] = {
|
|
.name = "else", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_ENDIF] = {
|
|
.name = "endif", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[38] = {
|
|
.table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
|
|
},
|
|
[BRW_OPCODE_WHILE] = {
|
|
.name = "while", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_BREAK] = {
|
|
.name = "break", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_CONTINUE] = {
|
|
.name = "cont", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_HALT] = {
|
|
.name = "halt", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[43] = {
|
|
.name = "calla", .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
|
|
},
|
|
[44] = {
|
|
.table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
|
|
},
|
|
[45] = {
|
|
.table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
|
|
},
|
|
[46] = {
|
|
.table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
|
|
},
|
|
[47] = {
|
|
.name = "pop", .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
|
|
},
|
|
[BRW_OPCODE_WAIT] = {
|
|
.name = "wait", .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SEND] = {
|
|
.name = "send", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SENDC] = {
|
|
.name = "sendc", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SENDS] = {
|
|
.name = "sends", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
|
|
},
|
|
[BRW_OPCODE_SENDSC] = {
|
|
.name = "sendsc", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
|
|
},
|
|
/* Reserved 53-55 */
|
|
[BRW_OPCODE_MATH] = {
|
|
.name = "math", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
|
|
},
|
|
/* Reserved 57-63 */
|
|
[BRW_OPCODE_ADD] = {
|
|
.name = "add", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_MUL] = {
|
|
.name = "mul", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_AVG] = {
|
|
.name = "avg", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_FRC] = {
|
|
.name = "frc", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_RNDU] = {
|
|
.name = "rndu", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_RNDD] = {
|
|
.name = "rndd", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_RNDE] = {
|
|
.name = "rnde", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_RNDZ] = {
|
|
.name = "rndz", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_MAC] = {
|
|
.name = "mac", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_MACH] = {
|
|
.name = "mach", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_LZD] = {
|
|
.name = "lzd", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_FBH] = {
|
|
.name = "fbh", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_FBL] = {
|
|
.name = "fbl", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_CBIT] = {
|
|
.name = "cbit", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_ADDC] = {
|
|
.name = "addc", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_SUBB] = {
|
|
.name = "subb", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
|
|
},
|
|
[BRW_OPCODE_SAD2] = {
|
|
.name = "sad2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_SADA2] = {
|
|
.name = "sada2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
/* Reserved 82-83 */
|
|
[BRW_OPCODE_DP4] = {
|
|
.name = "dp4", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_DPH] = {
|
|
.name = "dph", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_DP3] = {
|
|
.name = "dp3", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_DP2] = {
|
|
.name = "dp2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
/* Reserved 88 */
|
|
[BRW_OPCODE_LINE] = {
|
|
.name = "line", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
|
|
},
|
|
[BRW_OPCODE_PLN] = {
|
|
.name = "pln", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
|
|
},
|
|
[BRW_OPCODE_MAD] = {
|
|
.name = "mad", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
|
|
},
|
|
[BRW_OPCODE_LRP] = {
|
|
.name = "lrp", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
|
|
},
|
|
[93] = {
|
|
.name = "madm", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
|
|
},
|
|
/* Reserved 94-124 */
|
|
[BRW_OPCODE_NENOP] = {
|
|
.name = "nenop", .nsrc = 0, .ndst = 0, .gens = GEN45,
|
|
},
|
|
[BRW_OPCODE_NOP] = {
|
|
.name = "nop", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
|
|
},
|
|
};
|
|
|
|
static enum gen
|
|
gen_from_devinfo(const struct gen_device_info *devinfo)
|
|
{
|
|
switch (devinfo->gen) {
|
|
case 4: return devinfo->is_g4x ? GEN45 : GEN4;
|
|
case 5: return GEN5;
|
|
case 6: return GEN6;
|
|
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
|
|
case 8: return GEN8;
|
|
case 9: return GEN9;
|
|
case 10: return GEN10;
|
|
default:
|
|
unreachable("not reached");
|
|
}
|
|
}
|
|
|
|
/* Return the matching opcode_desc for the specified opcode number and
|
|
* hardware generation, or NULL if the opcode is not supported by the device.
|
|
*/
|
|
const struct opcode_desc *
|
|
brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
|
|
{
|
|
if (opcode >= ARRAY_SIZE(opcode_descs))
|
|
return NULL;
|
|
|
|
enum gen gen = gen_from_devinfo(devinfo);
|
|
if (opcode_descs[opcode].gens != 0) {
|
|
if ((opcode_descs[opcode].gens & gen) != 0) {
|
|
return &opcode_descs[opcode];
|
|
}
|
|
} else if (opcode_descs[opcode].table != NULL) {
|
|
const struct opcode_desc *table = opcode_descs[opcode].table;
|
|
for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
|
|
if ((table[i].gens & gen) != 0) {
|
|
return &table[i];
|
|
}
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|