Anuj Phogat f9e31a26d4 i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3 ...

v1: By Ben Widawsky <benjamin.widawsky@intel.com>
v2: v1 had an assert only for VS. Add the restriction for GS, HS and
    DS as well and make sure the allocated sizes are not multiple of 3.
v3: Move the entry_size checks in to compiler code (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

2017-06-09 16:02:59 -07:00

..

.gitignore

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brw_cfg.cpp

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brw_cfg.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_clip_line.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_point.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_tri.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_unfilled.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip_util.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_clip.h

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compile_clip.c

i965: Move clip program compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compile_sf.c

i965: Move SF compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_compiler.c

i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.

2017-06-05 23:32:40 -07:00

brw_compiler.h

i965/cnl: Update few assertions

2017-06-09 16:02:59 -07:00

brw_dead_control_flow.cpp

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brw_dead_control_flow.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_disasm.c

intel/compiler: Make brw_disasm take const assembly

2017-05-26 07:58:01 -07:00

brw_eu_compact.c

i965/cnl: Handle gen10 in switch cases across the driver

2017-06-09 16:02:59 -07:00

brw_eu_defines.h

i965: Move SF compilation to the compiler

2017-05-26 07:58:01 -07:00

brw_eu_emit.c

i965: Use correct VertStride on align16 instructions.

2017-04-14 14:56:09 -07:00

brw_eu_util.c

intel/compiler: whitespace cleanups

2017-03-13 11:16:35 +00:00

brw_eu_validate.c

i965: Allow brw_eu_validate to handle compact instructions

2017-05-15 11:42:56 -07:00

brw_eu.c

i965/cnl: Handle gen10 in switch cases across the driver

2017-06-09 16:02:59 -07:00

brw_eu.h

intel/compiler: Make brw_disasm take const assembly

2017-05-26 07:58:01 -07:00

brw_fs_builder.h

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brw_fs_cmod_propagation.cpp

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brw_fs_combine_constants.cpp

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brw_fs_copy_propagation.cpp

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brw_fs_cse.cpp

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brw_fs_dead_code_eliminate.cpp

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brw_fs_generator.cpp

i965: Pass pointer and end of assembly to brw_validate_instructions

2017-05-15 11:42:47 -07:00

brw_fs_live_variables.cpp

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brw_fs_live_variables.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_fs_lower_conversions.cpp

i965/fs: rename lower_d2x to lower_conversions

2017-04-14 14:56:07 -07:00

brw_fs_lower_pack.cpp

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brw_fs_nir.cpp

i965/fs: Move remapping of gl_PointSize to the NIR level

2017-05-09 15:08:06 -07:00

brw_fs_reg_allocate.cpp

intel/fs: Take into account amount of data read in spilling cost heuristic.

2017-04-24 11:01:40 -07:00

brw_fs_register_coalesce.cpp

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brw_fs_saturate_propagation.cpp

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brw_fs_sel_peephole.cpp

Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."

2017-04-14 14:56:07 -07:00

brw_fs_surface_builder.cpp

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brw_fs_surface_builder.h

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brw_fs_validate.cpp

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brw_fs_visitor.cpp

i965/fs: Lower gl_VertexID and friends to inputs at the NIR level

2017-05-09 15:07:47 -07:00

brw_fs.cpp

i965: Drop duplicate shadow variable.

2017-06-01 14:28:12 -07:00

brw_fs.h

i965/fs: Lower gl_VertexID and friends to inputs at the NIR level

2017-05-09 15:07:47 -07:00

brw_inst.h

tree-wide: remove trailing backslash

2017-06-07 01:18:09 +01:00

brw_interpolation_map.c

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brw_ir_allocator.h

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brw_ir_fs.h

i965/fs: add helper to retrieve instruction execution type

2017-04-14 14:56:07 -07:00

brw_ir_vec4.h

i965/vec4: don't do horizontal stride on some register file types

2017-04-14 14:56:09 -07:00

brw_nir_analyze_boolean_resolves.c

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brw_nir_attribute_workarounds.c

nir: Rework conversion opcodes

2017-03-14 07:36:40 -07:00

brw_nir_intrinsics.c

nir: Embed the shader_info in the nir_shader again

2017-05-09 15:07:47 -07:00

brw_nir_opt_peephole_ffma.c

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brw_nir_tcs_workarounds.c

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brw_nir_trig_workarounds.py

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brw_nir.c

i965/vec4: Use NIR to do GS input remapping

2017-05-09 15:08:07 -07:00

brw_nir.h

i965/vec4: Use NIR to do GS input remapping

2017-05-09 15:08:07 -07:00

brw_packed_float.c

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brw_predicated_break.cpp

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brw_reg.h

i965/fs: add helper to retrieve instruction execution type

2017-04-14 14:56:07 -07:00

brw_schedule_instructions.cpp

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brw_shader.cpp

i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

2017-06-09 16:02:59 -07:00

brw_shader.h

intel/compiler: consistently use ifndef guards over pragma once

2017-03-22 16:55:22 +00:00

brw_vec4_builder.h

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brw_vec4_cmod_propagation.cpp

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brw_vec4_copy_propagation.cpp

i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type

2017-04-14 14:56:08 -07:00

brw_vec4_cse.cpp

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brw_vec4_dead_code_eliminate.cpp

i965/vec4/dce: improve track of partial flag register writes

2017-04-14 14:56:09 -07:00

brw_vec4_generator.cpp

i965: Pass pointer and end of assembly to brw_validate_instructions

2017-05-15 11:42:47 -07:00

brw_vec4_gs_nir.cpp

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_gs_visitor.cpp

i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

2017-06-09 16:02:59 -07:00

brw_vec4_gs_visitor.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_live_variables.cpp

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brw_vec4_live_variables.h

i965/vec4: consider subregister offset in live variables

2017-04-14 14:56:08 -07:00

brw_vec4_nir.cpp

i965/vec4: fix swizzle and writemask when loading an uniform with constant offset

2017-05-18 06:49:54 +02:00

brw_vec4_reg_allocate.cpp

i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type

2017-04-14 14:56:08 -07:00

brw_vec4_surface_builder.cpp

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brw_vec4_surface_builder.h

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brw_vec4_tcs.cpp

i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

2017-06-09 16:02:59 -07:00

brw_vec4_tcs.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_tes.cpp

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_tes.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_visitor.cpp

i965/vec4: Use NIR remapping for VS attributes

2017-05-09 15:08:06 -07:00

brw_vec4_vs_visitor.cpp

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4_vs.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vec4.cpp

i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

2017-06-09 16:02:59 -07:00

brw_vec4.h

i965/vec4: Delete the system value infastructure

2017-05-09 15:08:07 -07:00

brw_vue_map.c

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brw_wm_iz.cpp

nir: Embed the shader_info in the nir_shader again

2017-05-09 15:07:47 -07:00

gen6_gs_visitor.cpp

i965: Move SOL PSIZ hacks from draw time to link time.

2017-06-01 00:08:29 -07:00

gen6_gs_visitor.h

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intel_asm_annotation.c

i965: Add a weak no-op nir_print_instr() symbol

2017-05-15 11:43:01 -07:00

intel_asm_annotation.h

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test_eu_compact.cpp

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test_eu_validate.cpp

i965: Fix test_eu_validate.cpp

2017-05-16 11:45:07 -07:00

test_fs_cmod_propagation.cpp

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test_fs_copy_propagation.cpp

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test_fs_saturate_propagation.cpp

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test_vec4_cmod_propagation.cpp

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test_vec4_copy_propagation.cpp

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test_vec4_register_coalesce.cpp

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test_vf_float_conversions.cpp

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