f0421099ef
So we have stack memory allocated. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7206>
686 lines
22 KiB
C
686 lines
22 KiB
C
/*
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* Copyright (C) 2020 Collabora Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors (Collabora):
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* Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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*/
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#ifndef __BIFROST_COMPILER_H
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#define __BIFROST_COMPILER_H
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#include "bifrost.h"
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#include "compiler/nir/nir.h"
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#include "panfrost/util/pan_ir.h"
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/* Bifrost opcodes are tricky -- the same op may exist on both FMA and
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* ADD with two completely different opcodes, and opcodes can be varying
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* length in some cases. Then we have different opcodes for int vs float
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* and then sometimes even for different typesizes. Further, virtually
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* every op has a number of flags which depend on the op. In constrast
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* to Midgard where you have a strict ALU/LDST/TEX division and within
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* ALU you have strict int/float and that's it... here it's a *lot* more
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* involved. As such, we use something much higher level for our IR,
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* encoding "classes" of operations, letting the opcode details get
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* sorted out at emit time.
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*
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* Please keep this list alphabetized. Please use a dictionary if you
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* don't know how to do that.
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*/
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enum bi_class {
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BI_ADD,
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BI_ATEST,
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BI_BRANCH,
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BI_CMP,
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BI_BLEND,
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BI_BITWISE,
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BI_COMBINE,
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BI_CONVERT,
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BI_CSEL,
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BI_DISCARD,
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BI_FMA,
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BI_FMOV,
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BI_FREXP,
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BI_IMATH,
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BI_LOAD,
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BI_LOAD_UNIFORM,
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BI_LOAD_ATTR,
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BI_LOAD_VAR,
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BI_LOAD_VAR_ADDRESS,
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BI_LOAD_TILE,
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BI_MINMAX,
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BI_MOV,
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BI_REDUCE_FMA,
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BI_SELECT,
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BI_STORE,
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BI_STORE_VAR,
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BI_SPECIAL, /* _FAST on supported GPUs */
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BI_TABLE,
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BI_TEXS,
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BI_TEXC,
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BI_TEXC_DUAL,
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BI_ROUND,
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BI_IMUL,
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BI_NUM_CLASSES
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};
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/* Properties of a class... */
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extern unsigned bi_class_props[BI_NUM_CLASSES];
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/* abs/neg/outmod valid for a float op */
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#define BI_MODS (1 << 0)
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/* Accepts a bi_cond */
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#define BI_CONDITIONAL (1 << 1)
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/* Accepts a bifrost_roundmode */
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#define BI_ROUNDMODE (1 << 2)
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/* Can be scheduled to FMA */
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#define BI_SCHED_FMA (1 << 3)
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/* Can be scheduled to ADD */
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#define BI_SCHED_ADD (1 << 4)
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/* Most ALU ops can do either, actually */
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#define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
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/* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
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* nopped out. Used for _FAST operations. */
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#define BI_SCHED_SLOW (1 << 5)
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/* Swizzling allowed for the 8/16-bit source */
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#define BI_SWIZZLABLE (1 << 6)
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/* For scheduling purposes this is a high latency instruction and must be at
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* the end of a clause. Implies ADD */
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#define BI_SCHED_HI_LATENCY (1 << 7)
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/* Intrinsic is vectorized and acts with `vector_channels` components */
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#define BI_VECTOR (1 << 8)
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/* Use a data register for src0/dest respectively, bypassing the usual
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* register accessor. */
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#define BI_DATA_REG_SRC (1 << 9)
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#define BI_DATA_REG_DEST (1 << 10)
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/* Quirk: cannot encode multiple abs on FMA in fp16 mode */
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#define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
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/* It can't get any worse than csel4... can it? */
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#define BIR_SRC_COUNT 4
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/* BI_LD_VARY */
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struct bi_load_vary {
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enum bifrost_interp_mode interp_mode;
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bool reuse;
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bool flat;
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};
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/* BI_BRANCH encoding the details of the branch itself as well as a pointer to
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* the target. We forward declare bi_block since this is mildly circular (not
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* strictly, but this order of the file makes more sense I think)
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*
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* We define our own enum of conditions since the conditions in the hardware
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* packed in crazy ways that would make manipulation unweildly (meaning changes
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* based on slot swapping, etc), so we defer dealing with that until emit time.
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* Likewise, we expose NIR types instead of the crazy branch types, although
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* the restrictions do eventually apply of course. */
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struct bi_block;
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/* Sync with gen-pack.py */
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enum bi_cond {
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BI_COND_ALWAYS = 0,
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BI_COND_LT,
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BI_COND_LE,
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BI_COND_GE,
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BI_COND_GT,
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BI_COND_EQ,
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BI_COND_NE,
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};
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/* Segments, as synced with ISA. Used as an immediate in LOAD/STORE
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* instructions for address calculation, and directly in SEG_ADD/SEG_SUB
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* instructions. */
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enum bi_segment {
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/* No segment (use global addressing, offset from GPU VA 0x0) */
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BI_SEGMENT_NONE = 1,
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/* Within workgroup local memory (shared memory). Relative to
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* wls_base_pointer in the draw's thread storage descriptor */
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BI_SEGMENT_WLS = 2,
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/* Within one of the bound uniform buffers. Low 32-bits are the index
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* within the uniform buffer; high 32-bits are the index of the uniform
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* buffer itself. Relative to the uniform_array_pointer indexed within
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* the draw's uniform remap table indexed by the high 32-bits. */
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BI_SEGMENT_UBO = 4,
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/* Within thread local storage (for spilling). Relative to
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* tls_base_pointer in the draw's thread storage descriptor */
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BI_SEGMENT_TLS = 7
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};
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/* Opcodes within a class */
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enum bi_minmax_op {
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BI_MINMAX_MIN,
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BI_MINMAX_MAX
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};
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enum bi_bitwise_op {
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BI_BITWISE_AND,
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BI_BITWISE_OR,
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BI_BITWISE_XOR
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};
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enum bi_imath_op {
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BI_IMATH_ADD,
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BI_IMATH_SUB,
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};
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enum bi_imul_op {
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BI_IMUL_IMUL,
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};
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enum bi_table_op {
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/* fp32 log2() with low precision, suitable for GL or half_log2() in
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* CL. In the first argument, takes x. Letting u be such that x =
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* 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
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* log2(u) / (u - 1). */
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BI_TABLE_LOG2_U_OVER_U_1_LOW,
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};
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enum bi_reduce_op {
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/* Takes two fp32 arguments and returns x + frexp(y). Used in
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* low-precision log2 argument reduction on newer models. */
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BI_REDUCE_ADD_FREXPM,
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};
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enum bi_frexp_op {
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BI_FREXPE_LOG,
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};
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enum bi_special_op {
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BI_SPECIAL_FRCP,
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BI_SPECIAL_FRSQ,
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/* fp32 exp2() with low precision, suitable for half_exp2() in CL or
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* exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
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* the second, it takes x itself. */
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BI_SPECIAL_EXP2_LOW,
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BI_SPECIAL_IABS,
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};
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struct bi_bitwise {
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bool dest_invert;
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bool src1_invert;
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bool rshift; /* false for lshift */
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};
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struct bi_texture {
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/* Constant indices. Indirect would need to be in src[..] like normal,
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* we can reserve some sentinels there for that for future. */
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unsigned texture_index, sampler_index;
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/* Should the LOD be computed based on neighboring pixels? Only valid
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* in fragment shaders. */
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bool compute_lod;
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};
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typedef struct {
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struct list_head link; /* Must be first */
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enum bi_class type;
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/* Indices, see pan_ssa_index etc. Note zero is special cased
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* to "no argument" */
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unsigned dest;
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unsigned src[BIR_SRC_COUNT];
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/* 32-bit word offset for destination, added to the register number in
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* RA when lowering combines */
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unsigned dest_offset;
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/* If one of the sources has BIR_INDEX_CONSTANT */
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union {
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uint64_t u64;
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uint32_t u32;
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uint16_t u16[2];
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uint8_t u8[4];
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} constant;
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/* Floating-point modifiers, type/class permitting. If not
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* allowed for the type/class, these are ignored. */
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enum bifrost_outmod outmod;
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bool src_abs[BIR_SRC_COUNT];
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bool src_neg[BIR_SRC_COUNT];
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/* Round mode (requires BI_ROUNDMODE) */
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enum bifrost_roundmode roundmode;
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/* Destination type. Usually the type of the instruction
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* itself, but if sources and destination have different
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* types, the type of the destination wins (so f2i would be
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* int). Zero if there is no destination. Bitsize included */
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nir_alu_type dest_type;
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/* Source types if required by the class */
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nir_alu_type src_types[BIR_SRC_COUNT];
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/* register_format if applicable */
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nir_alu_type format;
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/* If the source type is 8-bit or 16-bit such that SIMD is possible,
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* and the class has BI_SWIZZLABLE, this is a swizzle in the usual
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* sense. On non-SIMD instructions, it can be used for component
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* selection, so we don't have to special case extraction. */
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uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
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/* For VECTOR ops, how many channels are written? */
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unsigned vector_channels;
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/* For texture ops, the skip bit. Set if helper invocations can skip
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* the operation. That is, set if the result of this texture operation
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* is never used for cross-lane operation (including texture
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* coordinates and derivatives) as determined by data flow analysis
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* (like Midgard) */
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bool skip;
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/* The comparison op. BI_COND_ALWAYS may not be valid. */
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enum bi_cond cond;
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/* For memory ops, base address */
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enum bi_segment segment;
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/* Can we spill the value written here? Used to prevent
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* useless double fills */
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bool no_spill;
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/* A class-specific op from which the actual opcode can be derived
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* (along with the above information) */
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union {
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enum bi_minmax_op minmax;
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enum bi_bitwise_op bitwise;
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enum bi_special_op special;
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enum bi_reduce_op reduce;
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enum bi_table_op table;
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enum bi_frexp_op frexp;
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enum bi_imath_op imath;
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enum bi_imul_op imul;
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/* For FMA/ADD, should we add a biased exponent? */
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bool mscale;
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} op;
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/* Union for class-specific information */
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union {
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enum bifrost_minmax_mode minmax;
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struct bi_load_vary load_vary;
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struct bi_block *branch_target;
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/* For BLEND -- the location 0-7 */
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unsigned blend_location;
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struct bi_bitwise bitwise;
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struct bi_texture texture;
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};
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} bi_instruction;
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/* Represents the assignment of slots for a given bi_bundle */
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typedef struct {
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/* Register to assign to each slot */
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unsigned slot[4];
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/* Read slots can be disabled */
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bool enabled[2];
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/* Configuration for slots 2/3 */
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struct bifrost_reg_ctrl_23 slot23;
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/* Fast-Access-Uniform RAM index */
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uint8_t fau_idx;
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/* Whether writes are actually for the last instruction */
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bool first_instruction;
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} bi_registers;
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/* A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
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* leave it NULL; the emitter will fill in a nop. Instructions reference
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* registers via slots which are assigned per bundle.
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*/
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typedef struct {
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uint8_t fau_idx;
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bi_registers regs;
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bi_instruction *fma;
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bi_instruction *add;
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} bi_bundle;
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struct bi_block;
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typedef struct {
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struct list_head link;
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/* Link back up for branch calculations */
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struct bi_block *block;
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/* A clause can have 8 instructions in bundled FMA/ADD sense, so there
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* can be 8 bundles. */
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unsigned bundle_count;
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bi_bundle bundles[8];
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/* For scoreboarding -- the clause ID (this is not globally unique!)
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* and its dependencies in terms of other clauses, computed during
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* scheduling and used when emitting code. Dependencies expressed as a
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* bitfield matching the hardware, except shifted by a clause (the
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* shift back to the ISA's off-by-one encoding is worked out when
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* emitting clauses) */
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unsigned scoreboard_id;
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uint8_t dependencies;
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/* See ISA header for description */
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enum bifrost_flow flow_control;
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/* Can we prefetch the next clause? Usually it makes sense, except for
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* clauses ending in unconditional branches */
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bool next_clause_prefetch;
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/* Assigned data register */
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unsigned staging_register;
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/* Corresponds to the usual bit but shifted by a clause */
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bool staging_barrier;
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/* Constants read by this clause. ISA limit. Must satisfy:
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*
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* constant_count + bundle_count <= 13
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*
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* Also implicitly constant_count <= bundle_count since a bundle only
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* reads a single constant.
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*/
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uint64_t constants[8];
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unsigned constant_count;
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/* Branches encode a constant offset relative to the program counter
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* with some magic flags. By convention, if there is a branch, its
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* constant will be last. Set this flag to indicate this is required.
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*/
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bool branch_constant;
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/* What type of high latency instruction is here, basically */
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unsigned message_type;
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} bi_clause;
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typedef struct bi_block {
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pan_block base; /* must be first */
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/* If true, uses clauses; if false, uses instructions */
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bool scheduled;
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struct list_head clauses; /* list of bi_clause */
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} bi_block;
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typedef struct {
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nir_shader *nir;
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gl_shader_stage stage;
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struct list_head blocks; /* list of bi_block */
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struct panfrost_sysvals sysvals;
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uint32_t quirks;
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unsigned tls_size;
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/* Is internally a blend shader? Depends on stage == FRAGMENT */
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bool is_blend;
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/* Blend constants */
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float blend_constants[4];
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/* Blend return offsets */
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uint32_t blend_ret_offsets[8];
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/* Blend tile buffer conversion desc */
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uint64_t blend_desc;
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/* During NIR->BIR */
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nir_function_impl *impl;
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bi_block *current_block;
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bi_block *after_block;
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bi_block *break_block;
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bi_block *continue_block;
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bool emitted_atest;
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nir_alu_type *blend_types;
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/* For creating temporaries */
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unsigned temp_alloc;
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/* Analysis results */
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bool has_liveness;
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/* Stats for shader-db */
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unsigned instruction_count;
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unsigned loop_count;
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unsigned spills;
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unsigned fills;
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} bi_context;
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static inline bi_instruction *
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bi_emit(bi_context *ctx, bi_instruction ins)
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{
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bi_instruction *u = rzalloc(ctx, bi_instruction);
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memcpy(u, &ins, sizeof(ins));
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list_addtail(&u->link, &ctx->current_block->base.instructions);
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return u;
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}
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static inline bi_instruction *
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bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
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{
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bi_instruction *u = rzalloc(ctx, bi_instruction);
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memcpy(u, &ins, sizeof(ins));
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list_addtail(&u->link, &tag->link);
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return u;
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}
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static inline void
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bi_remove_instruction(bi_instruction *ins)
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{
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list_del(&ins->link);
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}
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/* If high bits are set, instead of SSA/registers, we have specials indexed by
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* the low bits if necessary.
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*
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* Fixed register: do not allocate register, do not collect $200.
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* Uniform: access a uniform register given by low bits.
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* Constant: access the specified constant (specifies a bit offset / shift)
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* Zero: special cased to avoid wasting a constant
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* Passthrough: a bifrost_packed_src to passthrough T/T0/T1
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*/
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#define BIR_INDEX_REGISTER (1 << 31)
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#define BIR_INDEX_UNIFORM (1 << 30)
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#define BIR_INDEX_CONSTANT (1 << 29)
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#define BIR_INDEX_ZERO (1 << 28)
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#define BIR_INDEX_PASS (1 << 27)
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#define BIR_INDEX_BLEND (1 << 26)
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/* Keep me synced please so we can check src & BIR_SPECIAL */
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#define BIR_SPECIAL (BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM | \
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BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | \
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BIR_INDEX_PASS | BIR_INDEX_BLEND)
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static inline unsigned
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bi_max_temp(bi_context *ctx)
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{
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unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
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return ((alloc + 2 + ctx->temp_alloc) << 1);
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}
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static inline unsigned
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bi_make_temp(bi_context *ctx)
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{
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return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
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}
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static inline unsigned
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bi_make_temp_reg(bi_context *ctx)
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{
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return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
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}
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/* Iterators for Bifrost IR */
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#define bi_foreach_block(ctx, v) \
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list_for_each_entry(pan_block, v, &ctx->blocks, link)
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#define bi_foreach_block_from(ctx, from, v) \
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list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
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#define bi_foreach_block_from_rev(ctx, from, v) \
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list_for_each_entry_from_rev(pan_block, v, from, &ctx->blocks, link)
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#define bi_foreach_instr_in_block(block, v) \
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list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
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#define bi_foreach_instr_in_block_rev(block, v) \
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list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
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#define bi_foreach_instr_in_block_safe(block, v) \
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list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
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#define bi_foreach_instr_in_block_safe_rev(block, v) \
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list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
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#define bi_foreach_instr_in_block_from(block, v, from) \
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list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
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#define bi_foreach_instr_in_block_from_rev(block, v, from) \
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list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
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#define bi_foreach_clause_in_block(block, v) \
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list_for_each_entry(bi_clause, v, &(block)->clauses, link)
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#define bi_foreach_clause_in_block_safe(block, v) \
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list_for_each_entry_safe(bi_clause, v, &(block)->clauses, link)
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#define bi_foreach_clause_in_block_from(block, v, from) \
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list_for_each_entry_from(bi_clause, v, from, &(block)->clauses, link)
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#define bi_foreach_clause_in_block_from_rev(block, v, from) \
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list_for_each_entry_from_rev(bi_clause, v, from, &(block)->clauses, link)
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#define bi_foreach_instr_global(ctx, v) \
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bi_foreach_block(ctx, v_block) \
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bi_foreach_instr_in_block((bi_block *) v_block, v)
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#define bi_foreach_instr_global_safe(ctx, v) \
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bi_foreach_block(ctx, v_block) \
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bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
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/* Based on set_foreach, expanded with automatic type casts */
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#define bi_foreach_predecessor(blk, v) \
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struct set_entry *_entry_##v; \
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bi_block *v; \
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for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
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v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
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_entry_##v != NULL; \
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_entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
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v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
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#define bi_foreach_src(ins, v) \
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for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
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static inline bi_instruction *
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bi_prev_op(bi_instruction *ins)
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{
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return list_last_entry(&(ins->link), bi_instruction, link);
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}
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static inline bi_instruction *
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bi_next_op(bi_instruction *ins)
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{
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return list_first_entry(&(ins->link), bi_instruction, link);
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}
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static inline pan_block *
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pan_next_block(pan_block *block)
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{
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return list_first_entry(&(block->link), pan_block, link);
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}
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/* Special functions */
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void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr);
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void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr);
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/* BIR manipulation */
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bool bi_has_outmod(bi_instruction *ins);
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bool bi_has_source_mods(bi_instruction *ins);
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bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
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|
bool bi_has_arg(bi_instruction *ins, unsigned arg);
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uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
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unsigned bi_get_component_count(bi_instruction *ins, signed s);
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uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
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uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
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bool bi_writes_component(bi_instruction *ins, unsigned comp);
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unsigned bi_writemask(bi_instruction *ins);
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void bi_rewrite_uses(bi_context *ctx, unsigned old, unsigned oldc, unsigned new, unsigned newc);
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|
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/* BIR passes */
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|
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void bi_lower_combine(bi_context *ctx, bi_block *block);
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|
bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
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|
void bi_schedule(bi_context *ctx);
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|
void bi_register_allocate(bi_context *ctx);
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|
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bi_clause *bi_make_singleton(void *memctx, bi_instruction *ins,
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|
bi_block *block,
|
|
unsigned scoreboard_id,
|
|
unsigned dependencies,
|
|
bool osrb);
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|
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/* Liveness */
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|
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void bi_compute_liveness(bi_context *ctx);
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void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
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void bi_invalidate_liveness(bi_context *ctx);
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bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
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|
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/* Layout */
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bool bi_can_insert_bundle(bi_clause *clause, bool constant);
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|
unsigned bi_clause_quadwords(bi_clause *clause);
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|
signed bi_block_offset(bi_context *ctx, bi_clause *start, bi_block *target);
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|
|
/* Code emit */
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|
|
void bi_pack(bi_context *ctx, struct util_dynarray *emission);
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|
|
#endif
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