
On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented
using a separte cmpn and sel instruction. This lowering occurs in
fs_vistor::lower_minmax which is called very, very late... a long, long
time after the first calls to opt_cmod_propagation. As a result,
conditional modifiers can be incorrectly propagated across sel.cond on
those platforms.
No tests were affected by this change, and I find that quite shocking.
After just changing flags_written(), all of the atan tests started
failing on ILK. That required the change in cmod_propagatin (and the
addition of the prop_across_into_sel_gfx5 unit test).
Shader-db results for ILK and GM45 are below. I looked at a couple
before and after shaders... and every case that I looked at had
experienced incorrect cmod propagation. This affected a LOT of apps!
Euro Truck Simulator 2, The Talos Principle, Serious Sam 3, Sanctum 2,
Gang Beasts, and on and on... :(
I discovered this bug while working on a couple new optimization
passes. One of the passes attempts to remove condition modifiers that
are never used. The pass made no progress except on ILK and GM45.
After investigating a couple of the affected shaders, I noticed that
the code in those shaders looked wrong... investigation led to this
cause.
v2: Trivial changes in the unit tests.
v3: Fix type in comment in unit tests. Noticed by Jason and Priit.
v4: Tweak handling of BRW_OPCODE_SEL special case. Suggested by Jason.
Fixes: df1aec763e
("i965/fs: Define methods to calculate the flag subset read or written by an fs_inst.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Dave Airlie <airlied@redhat.com>
Iron Lake
total instructions in shared programs: 8180493 -> 8181781 (0.02%)
instructions in affected programs: 541796 -> 543084 (0.24%)
helped: 28
HURT: 1158
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.86% x̄: 0.53% x̃: 0.50%
HURT stats (abs) min: 1 max: 3 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.12% max: 4.00% x̄: 0.37% x̃: 0.23%
95% mean confidence interval for instructions value: 1.06 1.11
95% mean confidence interval for instructions %-change: 0.31% 0.38%
Instructions are HURT.
total cycles in shared programs: 239420470 -> 239421690 (<.01%)
cycles in affected programs: 2925992 -> 2927212 (0.04%)
helped: 49
HURT: 157
helped stats (abs) min: 2 max: 284 x̄: 62.69 x̃: 70
helped stats (rel) min: 0.04% max: 6.20% x̄: 1.68% x̃: 1.96%
HURT stats (abs) min: 2 max: 48 x̄: 27.34 x̃: 24
HURT stats (rel) min: 0.02% max: 2.91% x̄: 0.31% x̃: 0.20%
95% mean confidence interval for cycles value: -0.80 12.64
95% mean confidence interval for cycles %-change: -0.31% <.01%
Inconclusive result (value mean confidence interval includes 0).
GM45
total instructions in shared programs: 4985517 -> 4986207 (0.01%)
instructions in affected programs: 306935 -> 307625 (0.22%)
helped: 14
HURT: 625
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 0.82% x̄: 0.52% x̃: 0.49%
HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1
HURT stats (rel) min: 0.12% max: 3.90% x̄: 0.34% x̃: 0.22%
95% mean confidence interval for instructions value: 1.04 1.12
95% mean confidence interval for instructions %-change: 0.29% 0.36%
Instructions are HURT.
total cycles in shared programs: 153827268 -> 153828052 (<.01%)
cycles in affected programs: 1669290 -> 1670074 (0.05%)
helped: 24
HURT: 84
helped stats (abs) min: 2 max: 232 x̄: 64.33 x̃: 67
helped stats (rel) min: 0.04% max: 4.62% x̄: 1.60% x̃: 1.94%
HURT stats (abs) min: 2 max: 48 x̄: 27.71 x̃: 24
HURT stats (rel) min: 0.02% max: 2.66% x̄: 0.34% x̃: 0.14%
95% mean confidence interval for cycles value: -1.94 16.46
95% mean confidence interval for cycles %-change: -0.29% 0.11%
Inconclusive result (value mean confidence interval includes 0).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12191>
229 lines
7.3 KiB
C++
229 lines
7.3 KiB
C++
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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/** @file brw_fs_sel_peephole.cpp
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*
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* This file contains the opt_peephole_sel() optimization pass that replaces
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* MOV instructions to the same destination in the "then" and "else" bodies of
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* an if statement with SEL instructions.
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*/
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/* Four MOVs seems to be pretty typical, so I picked the next power of two in
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* the hopes that it would handle almost anything possible in a single
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* pass.
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*/
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#define MAX_MOVS 8 /**< The maximum number of MOVs to attempt to match. */
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using namespace brw;
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/**
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* Scans forwards from an IF counting consecutive MOV instructions in the
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* "then" and "else" blocks of the if statement.
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*
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* A pointer to the bblock_t following the IF is passed as the <then_block>
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* argument. The function stores pointers to the MOV instructions in the
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* <then_mov> and <else_mov> arrays.
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*
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* \return the minimum number of MOVs found in the two branches or zero if
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* an error occurred.
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*
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* E.g.:
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* IF ...
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* then_mov[0] = MOV g4, ...
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* then_mov[1] = MOV g5, ...
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* then_mov[2] = MOV g6, ...
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* ELSE ...
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* else_mov[0] = MOV g4, ...
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* else_mov[1] = MOV g5, ...
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* else_mov[2] = MOV g7, ...
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* ENDIF
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* returns 3.
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*/
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static int
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count_movs_from_if(const intel_device_info *devinfo,
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fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS],
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bblock_t *then_block, bblock_t *else_block)
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{
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int then_movs = 0;
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foreach_inst_in_block(fs_inst, inst, then_block) {
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if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
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inst->flags_written(devinfo))
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break;
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then_mov[then_movs] = inst;
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then_movs++;
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}
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int else_movs = 0;
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foreach_inst_in_block(fs_inst, inst, else_block) {
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if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
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inst->flags_written(devinfo))
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break;
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else_mov[else_movs] = inst;
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else_movs++;
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}
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return MIN2(then_movs, else_movs);
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}
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/**
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* Try to replace IF/MOV+/ELSE/MOV+/ENDIF with SEL.
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*
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* Many GLSL shaders contain the following pattern:
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*
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* x = condition ? foo : bar
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*
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* or
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*
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* if (...) a.xyzw = foo.xyzw;
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* else a.xyzw = bar.xyzw;
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*
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* The compiler emits an ir_if tree for this, since each subexpression might be
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* a complex tree that could have side-effects or short-circuit logic.
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*
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* However, the common case is to simply select one of two constants or
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* variable values---which is exactly what SEL is for. In this case, the
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* assembly looks like:
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*
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* (+f0) IF
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* MOV dst src0
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* ...
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* ELSE
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* MOV dst src1
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* ...
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* ENDIF
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*
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* where each pair of MOVs to a common destination and can be easily translated
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* into
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*
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* (+f0) SEL dst src0 src1
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*
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* If src0 is an immediate value, we promote it to a temporary GRF.
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*/
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bool
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fs_visitor::opt_peephole_sel()
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{
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bool progress = false;
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foreach_block (block, cfg) {
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/* IF instructions, by definition, can only be found at the ends of
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* basic blocks.
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*/
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fs_inst *if_inst = (fs_inst *)block->end();
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if (if_inst->opcode != BRW_OPCODE_IF)
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continue;
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fs_inst *else_mov[MAX_MOVS] = { NULL };
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fs_inst *then_mov[MAX_MOVS] = { NULL };
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bblock_t *then_block = block->next();
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bblock_t *else_block = NULL;
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foreach_list_typed(bblock_link, child, link, &block->children) {
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if (child->block != then_block) {
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if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) {
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else_block = child->block;
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}
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break;
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}
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}
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if (else_block == NULL)
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continue;
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int movs = count_movs_from_if(devinfo, then_mov, else_mov, then_block, else_block);
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if (movs == 0)
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continue;
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/* Generate SEL instructions for pairs of MOVs to a common destination. */
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for (int i = 0; i < movs; i++) {
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if (!then_mov[i] || !else_mov[i])
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break;
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/* Check that the MOVs are the right form. */
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if (!then_mov[i]->dst.equals(else_mov[i]->dst) ||
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then_mov[i]->exec_size != else_mov[i]->exec_size ||
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then_mov[i]->group != else_mov[i]->group ||
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then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all ||
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then_mov[i]->is_partial_write() ||
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else_mov[i]->is_partial_write() ||
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then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE ||
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else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) {
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movs = i;
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break;
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}
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/* Check that source types for mov operations match. */
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if (then_mov[i]->src[0].type != else_mov[i]->src[0].type) {
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movs = i;
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break;
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}
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}
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if (movs == 0)
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continue;
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for (int i = 0; i < movs; i++) {
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const fs_builder ibld = fs_builder(this, then_block, then_mov[i])
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.at(block, if_inst);
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if (then_mov[i]->src[0].equals(else_mov[i]->src[0])) {
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ibld.MOV(then_mov[i]->dst, then_mov[i]->src[0]);
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} else {
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/* Only the last source register can be a constant, so if the MOV
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* in the "then" clause uses a constant, we need to put it in a
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* temporary.
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*/
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fs_reg src0(then_mov[i]->src[0]);
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if (src0.file == IMM) {
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src0 = ibld.vgrf(then_mov[i]->src[0].type);
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ibld.MOV(src0, then_mov[i]->src[0]);
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}
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/* 64-bit immediates can't be placed in src1. */
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fs_reg src1(else_mov[i]->src[0]);
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if (src1.file == IMM && type_sz(src1.type) == 8) {
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src1 = ibld.vgrf(else_mov[i]->src[0].type);
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ibld.MOV(src1, else_mov[i]->src[0]);
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}
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set_predicate_inv(if_inst->predicate, if_inst->predicate_inverse,
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ibld.SEL(then_mov[i]->dst, src0, src1));
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}
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then_mov[i]->remove(then_block);
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else_mov[i]->remove(else_block);
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}
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progress = true;
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}
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if (progress)
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invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
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return progress;
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}
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