ef2cf9cc3c
The next job from this client will turn it back on unless TF gets disabled, but we don't want the state to leak from this client to another (which causes GPU hangs).
657 lines
29 KiB
C
657 lines
29 KiB
C
/*
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* Copyright © 2014-2017 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/u_format.h"
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#include "util/u_half.h"
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#include "vc5_context.h"
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#include "broadcom/common/v3d_macros.h"
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#include "broadcom/cle/v3dx_pack.h"
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#include "broadcom/compiler/v3d_compiler.h"
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static uint8_t
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vc5_factor(enum pipe_blendfactor factor, bool dst_alpha_one)
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{
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/* We may get a bad blendfactor when blending is disabled. */
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if (factor == 0)
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return V3D_BLEND_FACTOR_ZERO;
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switch (factor) {
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case PIPE_BLENDFACTOR_ZERO:
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return V3D_BLEND_FACTOR_ZERO;
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case PIPE_BLENDFACTOR_ONE:
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return V3D_BLEND_FACTOR_ONE;
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case PIPE_BLENDFACTOR_SRC_COLOR:
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return V3D_BLEND_FACTOR_SRC_COLOR;
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case PIPE_BLENDFACTOR_INV_SRC_COLOR:
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return V3D_BLEND_FACTOR_INV_SRC_COLOR;
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case PIPE_BLENDFACTOR_DST_COLOR:
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return V3D_BLEND_FACTOR_DST_COLOR;
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case PIPE_BLENDFACTOR_INV_DST_COLOR:
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return V3D_BLEND_FACTOR_INV_DST_COLOR;
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case PIPE_BLENDFACTOR_SRC_ALPHA:
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return V3D_BLEND_FACTOR_SRC_ALPHA;
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case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
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return V3D_BLEND_FACTOR_INV_SRC_ALPHA;
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case PIPE_BLENDFACTOR_DST_ALPHA:
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return (dst_alpha_one ?
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V3D_BLEND_FACTOR_ONE :
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V3D_BLEND_FACTOR_DST_ALPHA);
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case PIPE_BLENDFACTOR_INV_DST_ALPHA:
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return (dst_alpha_one ?
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V3D_BLEND_FACTOR_ZERO :
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V3D_BLEND_FACTOR_INV_DST_ALPHA);
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case PIPE_BLENDFACTOR_CONST_COLOR:
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return V3D_BLEND_FACTOR_CONST_COLOR;
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case PIPE_BLENDFACTOR_INV_CONST_COLOR:
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return V3D_BLEND_FACTOR_INV_CONST_COLOR;
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case PIPE_BLENDFACTOR_CONST_ALPHA:
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return V3D_BLEND_FACTOR_CONST_ALPHA;
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case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
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return V3D_BLEND_FACTOR_INV_CONST_ALPHA;
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case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
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return V3D_BLEND_FACTOR_SRC_ALPHA_SATURATE;
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default:
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unreachable("Bad blend factor");
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}
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}
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static inline uint16_t
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swizzled_border_color(const struct v3d_device_info *devinfo,
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struct pipe_sampler_state *sampler,
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struct vc5_sampler_view *sview,
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int chan)
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{
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const struct util_format_description *desc =
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util_format_description(sview->base.format);
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uint8_t swiz = chan;
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/* If we're doing swizzling in the sampler, then only rearrange the
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* border color for the mismatch between the VC5 texture format and
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* the PIPE_FORMAT, since GL_ARB_texture_swizzle will be handled by
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* the sampler's swizzle.
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*
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* For swizzling in the shader, we don't do any pre-swizzling of the
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* border color.
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*/
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if (vc5_get_tex_return_size(devinfo, sview->base.format,
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sampler->compare_mode) != 32)
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swiz = desc->swizzle[swiz];
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switch (swiz) {
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case PIPE_SWIZZLE_0:
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return util_float_to_half(0.0);
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case PIPE_SWIZZLE_1:
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return util_float_to_half(1.0);
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default:
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return util_float_to_half(sampler->border_color.f[swiz]);
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}
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}
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#if V3D_VERSION < 40
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static uint32_t
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translate_swizzle(unsigned char pipe_swizzle)
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{
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switch (pipe_swizzle) {
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case PIPE_SWIZZLE_0:
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return 0;
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case PIPE_SWIZZLE_1:
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return 1;
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case PIPE_SWIZZLE_X:
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case PIPE_SWIZZLE_Y:
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case PIPE_SWIZZLE_Z:
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case PIPE_SWIZZLE_W:
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return 2 + pipe_swizzle;
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default:
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unreachable("unknown swizzle");
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}
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}
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static void
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emit_one_texture(struct vc5_context *vc5, struct vc5_texture_stateobj *stage_tex,
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int i)
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{
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struct vc5_job *job = vc5->job;
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struct pipe_sampler_state *psampler = stage_tex->samplers[i];
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struct vc5_sampler_state *sampler = vc5_sampler_state(psampler);
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struct pipe_sampler_view *psview = stage_tex->textures[i];
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struct vc5_sampler_view *sview = vc5_sampler_view(psview);
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struct pipe_resource *prsc = psview->texture;
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struct vc5_resource *rsc = vc5_resource(prsc);
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const struct v3d_device_info *devinfo = &vc5->screen->devinfo;
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stage_tex->texture_state[i].offset =
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vc5_cl_ensure_space(&job->indirect,
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cl_packet_length(TEXTURE_SHADER_STATE),
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32);
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vc5_bo_set_reference(&stage_tex->texture_state[i].bo,
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job->indirect.bo);
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uint32_t return_size = vc5_get_tex_return_size(devinfo, psview->format,
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psampler->compare_mode);
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struct V3D33_TEXTURE_SHADER_STATE unpacked = {
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/* XXX */
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.border_color_red = swizzled_border_color(devinfo, psampler,
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sview, 0),
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.border_color_green = swizzled_border_color(devinfo, psampler,
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sview, 1),
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.border_color_blue = swizzled_border_color(devinfo, psampler,
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sview, 2),
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.border_color_alpha = swizzled_border_color(devinfo, psampler,
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sview, 3),
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/* In the normal texturing path, the LOD gets clamped between
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* min/max, and the base_level field (set in the sampler view
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* from first_level) only decides where the min/mag switch
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* happens, so we need to use the LOD clamps to keep us
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* between min and max.
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*
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* For txf, the LOD clamp is still used, despite GL not
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* wanting that. We will need to have a separate
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* TEXTURE_SHADER_STATE that ignores psview->min/max_lod to
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* support txf properly.
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*/
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.min_level_of_detail = MIN2(psview->u.tex.first_level +
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MAX2(psampler->min_lod, 0),
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psview->u.tex.last_level),
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.max_level_of_detail = MIN2(psview->u.tex.first_level +
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psampler->max_lod,
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psview->u.tex.last_level),
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.texture_base_pointer = cl_address(rsc->bo,
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rsc->slices[0].offset),
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.output_32_bit = return_size == 32,
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};
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/* Set up the sampler swizzle if we're doing 16-bit sampling. For
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* 32-bit, we leave swizzling up to the shader compiler.
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*
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* Note: Contrary to the docs, the swizzle still applies even if the
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* return size is 32. It's just that you probably want to swizzle in
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* the shader, because you need the Y/Z/W channels to be defined.
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*/
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if (return_size == 32) {
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unpacked.swizzle_r = translate_swizzle(PIPE_SWIZZLE_X);
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unpacked.swizzle_g = translate_swizzle(PIPE_SWIZZLE_Y);
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unpacked.swizzle_b = translate_swizzle(PIPE_SWIZZLE_Z);
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unpacked.swizzle_a = translate_swizzle(PIPE_SWIZZLE_W);
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} else {
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unpacked.swizzle_r = translate_swizzle(sview->swizzle[0]);
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unpacked.swizzle_g = translate_swizzle(sview->swizzle[1]);
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unpacked.swizzle_b = translate_swizzle(sview->swizzle[2]);
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unpacked.swizzle_a = translate_swizzle(sview->swizzle[3]);
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}
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int min_img_filter = psampler->min_img_filter;
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int min_mip_filter = psampler->min_mip_filter;
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int mag_img_filter = psampler->mag_img_filter;
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if (return_size == 32) {
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min_mip_filter = PIPE_TEX_MIPFILTER_NEAREST;
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mag_img_filter = PIPE_TEX_FILTER_NEAREST;
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mag_img_filter = PIPE_TEX_FILTER_NEAREST;
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}
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bool min_nearest = min_img_filter == PIPE_TEX_FILTER_NEAREST;
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switch (min_mip_filter) {
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case PIPE_TEX_MIPFILTER_NONE:
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unpacked.filter += min_nearest ? 2 : 0;
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break;
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case PIPE_TEX_MIPFILTER_NEAREST:
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unpacked.filter += min_nearest ? 4 : 8;
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break;
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case PIPE_TEX_MIPFILTER_LINEAR:
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unpacked.filter += min_nearest ? 4 : 8;
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unpacked.filter += 2;
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break;
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}
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if (mag_img_filter == PIPE_TEX_FILTER_NEAREST)
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unpacked.filter++;
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if (psampler->max_anisotropy > 8)
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unpacked.filter = V3D_TMU_FILTER_ANISOTROPIC_16_1;
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else if (psampler->max_anisotropy > 4)
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unpacked.filter = V3D_TMU_FILTER_ANISOTROPIC_8_1;
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else if (psampler->max_anisotropy > 2)
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unpacked.filter = V3D_TMU_FILTER_ANISOTROPIC_4_1;
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else if (psampler->max_anisotropy)
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unpacked.filter = V3D_TMU_FILTER_ANISOTROPIC_2_1;
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uint8_t packed[cl_packet_length(TEXTURE_SHADER_STATE)];
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cl_packet_pack(TEXTURE_SHADER_STATE)(&job->indirect, packed, &unpacked);
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for (int i = 0; i < ARRAY_SIZE(packed); i++)
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packed[i] |= sview->texture_shader_state[i] | sampler->texture_shader_state[i];
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/* TMU indirect structs need to be 32b aligned. */
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vc5_cl_ensure_space(&job->indirect, ARRAY_SIZE(packed), 32);
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cl_emit_prepacked(&job->indirect, &packed);
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}
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static void
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emit_textures(struct vc5_context *vc5, struct vc5_texture_stateobj *stage_tex)
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{
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for (int i = 0; i < stage_tex->num_textures; i++) {
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if (stage_tex->textures[i])
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emit_one_texture(vc5, stage_tex, i);
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}
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}
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#endif /* V3D_VERSION < 40 */
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static uint32_t
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translate_colormask(struct vc5_context *vc5, uint32_t colormask, int rt)
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{
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if (vc5->swap_color_rb & (1 << rt)) {
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colormask = ((colormask & (2 | 8)) |
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((colormask & 1) << 2) |
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((colormask & 4) >> 2));
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}
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return (~colormask) & 0xf;
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}
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static void
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emit_rt_blend(struct vc5_context *vc5, struct vc5_job *job,
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struct pipe_blend_state *blend, int rt)
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{
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cl_emit(&job->bcl, BLEND_CONFIG, config) {
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struct pipe_rt_blend_state *rtblend = &blend->rt[rt];
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#if V3D_VERSION >= 40
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config.render_target_mask = 1 << rt;
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#else
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assert(rt == 0);
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#endif
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config.colour_blend_mode = rtblend->rgb_func;
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config.colour_blend_dst_factor =
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vc5_factor(rtblend->rgb_dst_factor,
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vc5->blend_dst_alpha_one);
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config.colour_blend_src_factor =
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vc5_factor(rtblend->rgb_src_factor,
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vc5->blend_dst_alpha_one);
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config.alpha_blend_mode = rtblend->alpha_func;
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config.alpha_blend_dst_factor =
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vc5_factor(rtblend->alpha_dst_factor,
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vc5->blend_dst_alpha_one);
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config.alpha_blend_src_factor =
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vc5_factor(rtblend->alpha_src_factor,
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vc5->blend_dst_alpha_one);
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}
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}
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void
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v3dX(emit_state)(struct pipe_context *pctx)
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{
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struct vc5_context *vc5 = vc5_context(pctx);
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struct vc5_job *job = vc5->job;
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if (vc5->dirty & (VC5_DIRTY_SCISSOR | VC5_DIRTY_VIEWPORT |
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VC5_DIRTY_RASTERIZER)) {
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float *vpscale = vc5->viewport.scale;
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float *vptranslate = vc5->viewport.translate;
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float vp_minx = -fabsf(vpscale[0]) + vptranslate[0];
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float vp_maxx = fabsf(vpscale[0]) + vptranslate[0];
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float vp_miny = -fabsf(vpscale[1]) + vptranslate[1];
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float vp_maxy = fabsf(vpscale[1]) + vptranslate[1];
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/* Clip to the scissor if it's enabled, but still clip to the
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* drawable regardless since that controls where the binner
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* tries to put things.
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*
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* Additionally, always clip the rendering to the viewport,
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* since the hardware does guardband clipping, meaning
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* primitives would rasterize outside of the view volume.
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*/
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uint32_t minx, miny, maxx, maxy;
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if (!vc5->rasterizer->base.scissor) {
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minx = MAX2(vp_minx, 0);
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miny = MAX2(vp_miny, 0);
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maxx = MIN2(vp_maxx, job->draw_width);
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maxy = MIN2(vp_maxy, job->draw_height);
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} else {
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minx = MAX2(vp_minx, vc5->scissor.minx);
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miny = MAX2(vp_miny, vc5->scissor.miny);
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maxx = MIN2(vp_maxx, vc5->scissor.maxx);
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maxy = MIN2(vp_maxy, vc5->scissor.maxy);
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}
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cl_emit(&job->bcl, CLIP_WINDOW, clip) {
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clip.clip_window_left_pixel_coordinate = minx;
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clip.clip_window_bottom_pixel_coordinate = miny;
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clip.clip_window_width_in_pixels = maxx - minx;
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clip.clip_window_height_in_pixels = maxy - miny;
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}
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job->draw_min_x = MIN2(job->draw_min_x, minx);
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job->draw_min_y = MIN2(job->draw_min_y, miny);
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job->draw_max_x = MAX2(job->draw_max_x, maxx);
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job->draw_max_y = MAX2(job->draw_max_y, maxy);
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}
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if (vc5->dirty & (VC5_DIRTY_RASTERIZER |
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VC5_DIRTY_ZSA |
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VC5_DIRTY_BLEND |
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VC5_DIRTY_COMPILED_FS)) {
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cl_emit(&job->bcl, CONFIGURATION_BITS, config) {
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config.enable_forward_facing_primitive =
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!vc5->rasterizer->base.rasterizer_discard &&
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!(vc5->rasterizer->base.cull_face &
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PIPE_FACE_FRONT);
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config.enable_reverse_facing_primitive =
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!vc5->rasterizer->base.rasterizer_discard &&
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!(vc5->rasterizer->base.cull_face &
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PIPE_FACE_BACK);
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/* This seems backwards, but it's what gets the
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* clipflat test to pass.
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*/
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config.clockwise_primitives =
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vc5->rasterizer->base.front_ccw;
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config.enable_depth_offset =
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vc5->rasterizer->base.offset_tri;
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config.rasterizer_oversample_mode =
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vc5->rasterizer->base.multisample;
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config.direct3d_provoking_vertex =
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vc5->rasterizer->base.flatshade_first;
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config.blend_enable = vc5->blend->rt[0].blend_enable;
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config.early_z_updates_enable = true;
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if (vc5->zsa->base.depth.enabled) {
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config.z_updates_enable =
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vc5->zsa->base.depth.writemask;
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config.early_z_enable =
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(vc5->zsa->early_z_enable &&
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!vc5->prog.fs->prog_data.fs->writes_z);
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config.depth_test_function =
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vc5->zsa->base.depth.func;
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} else {
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config.depth_test_function = PIPE_FUNC_ALWAYS;
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}
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config.stencil_enable =
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vc5->zsa->base.stencil[0].enabled;
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}
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}
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if (vc5->dirty & VC5_DIRTY_RASTERIZER &&
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vc5->rasterizer->base.offset_tri) {
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cl_emit(&job->bcl, DEPTH_OFFSET, depth) {
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depth.depth_offset_factor =
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vc5->rasterizer->offset_factor;
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depth.depth_offset_units =
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vc5->rasterizer->offset_units;
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}
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}
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if (vc5->dirty & VC5_DIRTY_RASTERIZER) {
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cl_emit(&job->bcl, POINT_SIZE, point_size) {
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point_size.point_size = vc5->rasterizer->point_size;
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}
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cl_emit(&job->bcl, LINE_WIDTH, line_width) {
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line_width.line_width = vc5->rasterizer->base.line_width;
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}
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}
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if (vc5->dirty & VC5_DIRTY_VIEWPORT) {
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cl_emit(&job->bcl, CLIPPER_XY_SCALING, clip) {
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clip.viewport_half_width_in_1_256th_of_pixel =
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vc5->viewport.scale[0] * 256.0f;
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clip.viewport_half_height_in_1_256th_of_pixel =
|
|
vc5->viewport.scale[1] * 256.0f;
|
|
}
|
|
|
|
cl_emit(&job->bcl, CLIPPER_Z_SCALE_AND_OFFSET, clip) {
|
|
clip.viewport_z_offset_zc_to_zs =
|
|
vc5->viewport.translate[2];
|
|
clip.viewport_z_scale_zc_to_zs =
|
|
vc5->viewport.scale[2];
|
|
}
|
|
cl_emit(&job->bcl, CLIPPER_Z_MIN_MAX_CLIPPING_PLANES, clip) {
|
|
clip.minimum_zw = (vc5->viewport.translate[2] -
|
|
vc5->viewport.scale[2]);
|
|
clip.maximum_zw = (vc5->viewport.translate[2] +
|
|
vc5->viewport.scale[2]);
|
|
}
|
|
|
|
cl_emit(&job->bcl, VIEWPORT_OFFSET, vp) {
|
|
vp.viewport_centre_x_coordinate =
|
|
vc5->viewport.translate[0];
|
|
vp.viewport_centre_y_coordinate =
|
|
vc5->viewport.translate[1];
|
|
}
|
|
}
|
|
|
|
if (vc5->dirty & VC5_DIRTY_BLEND && vc5->blend->rt[0].blend_enable) {
|
|
struct pipe_blend_state *blend = vc5->blend;
|
|
|
|
if (blend->independent_blend_enable) {
|
|
for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++)
|
|
emit_rt_blend(vc5, job, blend, i);
|
|
} else {
|
|
emit_rt_blend(vc5, job, blend, 0);
|
|
}
|
|
}
|
|
|
|
if (vc5->dirty & VC5_DIRTY_BLEND) {
|
|
struct pipe_blend_state *blend = vc5->blend;
|
|
|
|
cl_emit(&job->bcl, COLOUR_WRITE_MASKS, mask) {
|
|
if (blend->independent_blend_enable) {
|
|
mask.render_target_0_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[0].colormask, 0);
|
|
mask.render_target_1_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[1].colormask, 1);
|
|
mask.render_target_2_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[2].colormask, 2);
|
|
mask.render_target_3_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[3].colormask, 3);
|
|
} else {
|
|
mask.render_target_0_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[0].colormask, 0);
|
|
mask.render_target_1_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[0].colormask, 1);
|
|
mask.render_target_2_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[0].colormask, 2);
|
|
mask.render_target_3_per_colour_component_write_masks =
|
|
translate_colormask(vc5, blend->rt[0].colormask, 3);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (vc5->dirty & VC5_DIRTY_BLEND_COLOR) {
|
|
cl_emit(&job->bcl, BLEND_CONSTANT_COLOUR, colour) {
|
|
colour.red_f16 = (vc5->swap_color_rb ?
|
|
vc5->blend_color.hf[2] :
|
|
vc5->blend_color.hf[0]);
|
|
colour.green_f16 = vc5->blend_color.hf[1];
|
|
colour.blue_f16 = (vc5->swap_color_rb ?
|
|
vc5->blend_color.hf[0] :
|
|
vc5->blend_color.hf[2]);
|
|
colour.alpha_f16 = vc5->blend_color.hf[3];
|
|
}
|
|
}
|
|
|
|
if (vc5->dirty & (VC5_DIRTY_ZSA | VC5_DIRTY_STENCIL_REF)) {
|
|
struct pipe_stencil_state *front = &vc5->zsa->base.stencil[0];
|
|
struct pipe_stencil_state *back = &vc5->zsa->base.stencil[1];
|
|
|
|
if (front->enabled) {
|
|
cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
|
|
vc5->zsa->stencil_front, config) {
|
|
config.stencil_ref_value =
|
|
vc5->stencil_ref.ref_value[0];
|
|
}
|
|
}
|
|
|
|
if (back->enabled) {
|
|
cl_emit_with_prepacked(&job->bcl, STENCIL_CONFIG,
|
|
vc5->zsa->stencil_back, config) {
|
|
config.stencil_ref_value =
|
|
vc5->stencil_ref.ref_value[1];
|
|
}
|
|
}
|
|
}
|
|
|
|
#if V3D_VERSION < 40
|
|
/* Pre-4.x, we have texture state that depends on both the sampler and
|
|
* the view, so we merge them together at draw time.
|
|
*/
|
|
if (vc5->dirty & VC5_DIRTY_FRAGTEX)
|
|
emit_textures(vc5, &vc5->fragtex);
|
|
|
|
if (vc5->dirty & VC5_DIRTY_VERTTEX)
|
|
emit_textures(vc5, &vc5->verttex);
|
|
#endif
|
|
|
|
if (vc5->dirty & VC5_DIRTY_FLAT_SHADE_FLAGS) {
|
|
bool emitted_any = false;
|
|
|
|
for (int i = 0; i < ARRAY_SIZE(vc5->prog.fs->prog_data.fs->flat_shade_flags); i++) {
|
|
if (!vc5->prog.fs->prog_data.fs->flat_shade_flags[i])
|
|
continue;
|
|
|
|
cl_emit(&job->bcl, FLAT_SHADE_FLAGS, flags) {
|
|
flags.varying_offset_v0 = i;
|
|
|
|
if (emitted_any) {
|
|
flags.action_for_flat_shade_flags_of_lower_numbered_varyings =
|
|
V3D_VARYING_FLAGS_ACTION_UNCHANGED;
|
|
flags.action_for_flat_shade_flags_of_higher_numbered_varyings =
|
|
V3D_VARYING_FLAGS_ACTION_UNCHANGED;
|
|
} else {
|
|
flags.action_for_flat_shade_flags_of_lower_numbered_varyings =
|
|
((i == 0) ?
|
|
V3D_VARYING_FLAGS_ACTION_UNCHANGED :
|
|
V3D_VARYING_FLAGS_ACTION_ZEROED);
|
|
|
|
flags.action_for_flat_shade_flags_of_higher_numbered_varyings =
|
|
V3D_VARYING_FLAGS_ACTION_ZEROED;
|
|
}
|
|
|
|
flags.flat_shade_flags_for_varyings_v024 =
|
|
vc5->prog.fs->prog_data.fs->flat_shade_flags[i];
|
|
}
|
|
|
|
emitted_any = true;
|
|
}
|
|
|
|
if (!emitted_any) {
|
|
cl_emit(&job->bcl, ZERO_ALL_FLAT_SHADE_FLAGS, flags);
|
|
}
|
|
}
|
|
|
|
/* Set up the transform feedback data specs (which VPM entries to
|
|
* output to which buffers).
|
|
*/
|
|
if (vc5->dirty & (VC5_DIRTY_STREAMOUT |
|
|
VC5_DIRTY_RASTERIZER |
|
|
VC5_DIRTY_PRIM_MODE)) {
|
|
struct vc5_streamout_stateobj *so = &vc5->streamout;
|
|
|
|
if (so->num_targets) {
|
|
bool psiz_per_vertex = (vc5->prim_mode == PIPE_PRIM_POINTS &&
|
|
vc5->rasterizer->base.point_size_per_vertex);
|
|
uint16_t *tf_specs = (psiz_per_vertex ?
|
|
vc5->prog.bind_vs->tf_specs_psiz :
|
|
vc5->prog.bind_vs->tf_specs);
|
|
|
|
#if V3D_VERSION >= 40
|
|
job->tf_enabled = (vc5->prog.bind_vs->num_tf_specs != 0 &&
|
|
vc5->active_queries);
|
|
|
|
cl_emit(&job->bcl, TRANSFORM_FEEDBACK_SPECS, tfe) {
|
|
tfe.number_of_16_bit_output_data_specs_following =
|
|
vc5->prog.bind_vs->num_tf_specs;
|
|
tfe.enable = job->tf_enabled;
|
|
};
|
|
#else /* V3D_VERSION < 40 */
|
|
cl_emit(&job->bcl, TRANSFORM_FEEDBACK_ENABLE, tfe) {
|
|
tfe.number_of_32_bit_output_buffer_address_following =
|
|
so->num_targets;
|
|
tfe.number_of_16_bit_output_data_specs_following =
|
|
vc5->prog.bind_vs->num_tf_specs;
|
|
};
|
|
#endif /* V3D_VERSION < 40 */
|
|
for (int i = 0; i < vc5->prog.bind_vs->num_tf_specs; i++) {
|
|
cl_emit_prepacked(&job->bcl, &tf_specs[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set up the trasnform feedback buffers. */
|
|
if (vc5->dirty & VC5_DIRTY_STREAMOUT) {
|
|
struct vc5_streamout_stateobj *so = &vc5->streamout;
|
|
for (int i = 0; i < so->num_targets; i++) {
|
|
const struct pipe_stream_output_target *target =
|
|
so->targets[i];
|
|
struct vc5_resource *rsc = target ?
|
|
vc5_resource(target->buffer) : NULL;
|
|
|
|
#if V3D_VERSION >= 40
|
|
if (!target)
|
|
continue;
|
|
|
|
cl_emit(&job->bcl, TRANSFORM_FEEDBACK_BUFFER, output) {
|
|
output.buffer_address =
|
|
cl_address(rsc->bo,
|
|
target->buffer_offset);
|
|
output.buffer_size_in_32_bit_words =
|
|
target->buffer_size >> 2;
|
|
output.buffer_number = i;
|
|
}
|
|
#else /* V3D_VERSION < 40 */
|
|
cl_emit(&job->bcl, TRANSFORM_FEEDBACK_OUTPUT_ADDRESS, output) {
|
|
if (target) {
|
|
output.address =
|
|
cl_address(rsc->bo,
|
|
target->buffer_offset);
|
|
}
|
|
};
|
|
#endif /* V3D_VERSION < 40 */
|
|
if (target) {
|
|
vc5_job_add_write_resource(vc5->job,
|
|
target->buffer);
|
|
}
|
|
/* XXX: buffer_size? */
|
|
}
|
|
}
|
|
|
|
if (vc5->dirty & VC5_DIRTY_OQ) {
|
|
cl_emit(&job->bcl, OCCLUSION_QUERY_COUNTER, counter) {
|
|
job->oq_enabled = vc5->active_queries && vc5->current_oq;
|
|
if (job->oq_enabled) {
|
|
counter.address = cl_address(vc5->current_oq, 0);
|
|
}
|
|
}
|
|
}
|
|
}
|