e3e7ae732c
Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
129 lines
3.2 KiB
C++
129 lines
3.2 KiB
C++
//===-- AMDGPUUtil.cpp - TODO: Add brief description -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TODO: Add full description
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUUtil.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDIL.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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/* Some instructions act as place holders to emulate operations that the GPU
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* hardware does automatically. This function can be used to check if
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* an opcode falls into this category. */
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bool llvm::isPlaceHolderOpcode(unsigned opcode)
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{
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switch (opcode) {
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default: return false;
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case AMDIL::EXPORT_REG:
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case AMDIL::RETURN:
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case AMDIL::LOAD_INPUT:
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case AMDIL::LAST:
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case AMDIL::MASK_WRITE:
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case AMDIL::RESERVE_REG:
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return true;
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}
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}
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bool llvm::isTransOp(unsigned opcode)
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{
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switch(opcode) {
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default: return false;
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case AMDIL::COS_f32:
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case AMDIL::COS_r600:
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case AMDIL::COS_eg:
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case AMDIL::RSQ_f32:
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case AMDIL::FTOI:
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case AMDIL::ITOF:
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case AMDIL::MULLIT:
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case AMDIL::MUL_LIT_r600:
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case AMDIL::MUL_LIT_eg:
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case AMDIL::SHR_i32:
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case AMDIL::SIN_f32:
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case AMDIL::EXP_f32:
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case AMDIL::EXP_IEEE_r600:
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case AMDIL::EXP_IEEE_eg:
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case AMDIL::LOG_CLAMPED_r600:
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case AMDIL::LOG_IEEE_r600:
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case AMDIL::LOG_CLAMPED_eg:
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case AMDIL::LOG_IEEE_eg:
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case AMDIL::LOG_f32:
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return true;
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}
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}
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bool llvm::isTexOp(unsigned opcode)
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{
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switch(opcode) {
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default: return false;
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case AMDIL::TEX_SAMPLE:
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case AMDIL::TEX_SAMPLE_C:
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case AMDIL::TEX_SAMPLE_L:
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case AMDIL::TEX_SAMPLE_C_L:
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case AMDIL::TEX_SAMPLE_LB:
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case AMDIL::TEX_SAMPLE_C_LB:
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case AMDIL::TEX_SAMPLE_G:
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case AMDIL::TEX_SAMPLE_C_G:
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return true;
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}
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}
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bool llvm::isReductionOp(unsigned opcode)
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{
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switch(opcode) {
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default: return false;
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case AMDIL::DOT4_r600:
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case AMDIL::DOT4_eg:
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return true;
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}
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}
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bool llvm::isFCOp(unsigned opcode)
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{
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switch(opcode) {
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default: return false;
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case AMDIL::BREAK_LOGICALZ_f32:
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case AMDIL::BREAK_LOGICALNZ_i32:
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case AMDIL::BREAK_LOGICALZ_i32:
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case AMDIL::CONTINUE_LOGICALNZ_f32:
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case AMDIL::IF_LOGICALNZ_i32:
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case AMDIL::IF_LOGICALZ_f32:
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case AMDIL::ELSE:
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case AMDIL::ENDIF:
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case AMDIL::ENDLOOP:
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case AMDIL::IF_LOGICALNZ_f32:
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case AMDIL::WHILELOOP:
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return true;
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}
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}
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void AMDGPU::utilAddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
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const struct TargetInstrInfo * TII, unsigned physReg, unsigned virtReg)
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{
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if (!MRI.isLiveIn(physReg)) {
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MRI.addLiveIn(physReg, virtReg);
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MF->front().addLiveIn(physReg);
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BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
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TII->get(TargetOpcode::COPY), virtReg)
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.addReg(physReg);
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} else {
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MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
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}
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}
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