dc28390e3c
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "*gen[[:digit:]]*.*[cph]" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen/gfx}"' \;
grep -E "gen[[:digit:]]+_[[:alnum:]_]*\.(c|h|cpp)" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+_[[:alnum:]_]*\.\)\(c\|h\|cpp\)/gfx\1\2/g"
grep -E "_gen[[:digit:]]+[[:alnum:]_]*\.(c|h|cpp)" -rIl $SEARCH_PATH | xargs sed -ie "s/\(_\)gen\([[:digit:]]\+[[:alnum:]_]*\.\)\(c\|h\|cpp\)/\1gfx\2\3/g"
grep -E "GEN[[:digit:]]+[[:alnum:]_]*_H( |$)" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+[[:alnum:]_]*_H\)\( \|$\)/GFX\1\2/g"
Exclude the "_pack.h" changes:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
428 lines
16 KiB
C
428 lines
16 KiB
C
/*
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* Copyright 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "isl_gfx7.h"
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#include "isl_priv.h"
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static bool
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gen7_format_needs_valign2(const struct isl_device *dev,
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enum isl_format format)
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{
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assert(ISL_GFX_VER(dev) == 7);
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/* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
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* RENDER_SURFACE_STATE Surface Vertical Alignment:
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*
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* - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
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* (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
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* (0x190)
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*
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* - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
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*
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* The R32G32B32_FLOAT restriction is dropped on Haswell.
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*/
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return isl_format_is_yuv(format) ||
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(format == ISL_FORMAT_R32G32B32_FLOAT && !ISL_DEV_IS_HASWELL(dev));
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}
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bool
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isl_gen7_choose_msaa_layout(const struct isl_device *dev,
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const struct isl_surf_init_info *info,
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enum isl_tiling tiling,
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enum isl_msaa_layout *msaa_layout)
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{
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bool require_array = false;
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bool require_interleaved = false;
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assert(ISL_GFX_VER(dev) == 7);
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assert(info->samples >= 1);
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if (info->samples == 1) {
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*msaa_layout = ISL_MSAA_LAYOUT_NONE;
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return true;
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}
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if (!isl_format_supports_multisampling(dev->info, info->format))
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return false;
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/* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
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* Multisamples:
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*
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* - If this field is any value other than MULTISAMPLECOUNT_1, the
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* Surface Type must be SURFTYPE_2D.
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*
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* - If this field is any value other than MULTISAMPLECOUNT_1, Surface
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* Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
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*/
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if (info->dim != ISL_SURF_DIM_2D)
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return false;
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if (info->levels > 1)
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return false;
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/* The Ivyrbridge PRM insists twice that signed integer formats cannot be
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* multisampled.
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*
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* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
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* Multisamples:
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*
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* - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
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* all RT channels are not written.
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*
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* And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
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* RENDER_SURFACE_STATE, MCS Enable:
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*
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* This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
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* when all RT channels are not written.
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*
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* Note that the above SINT restrictions apply only to *MSRTs* (that is,
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* *multisampled* render targets). The restrictions seem to permit an MCS
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* if the render target is singlesampled.
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*
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* Moreover, empirically it looks that hardware can render multisampled
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* surfaces with RGBA8I, RGBA16I and RGBA32I.
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*/
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/* Multisampling requires vertical alignment of four. */
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if (info->samples > 1 && gen7_format_needs_valign2(dev, info->format))
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return false;
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/* More obvious restrictions */
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if (isl_surf_usage_is_display(info->usage))
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return false;
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if (tiling == ISL_TILING_LINEAR)
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return false;
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/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
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* Suface Storage Format:
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*
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* +---------------------+----------------------------------------------------------------+
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* | MSFMT_MSS | Multsampled surface was/is rendered as a render target |
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* | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
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* +---------------------+----------------------------------------------------------------+
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*
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* In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
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* MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
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*/
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if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
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(info->usage & ISL_SURF_USAGE_HIZ_BIT))
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require_interleaved = true;
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/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
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* Suface Storage Format:
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*
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* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
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* is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
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* field must be set to MSFMT_MSS.
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*/
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if (info->samples == 8 && info->width > 8192)
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require_array = true;
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/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
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* Suface Storage Format:
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*
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* If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
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* ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
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* of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
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* > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
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*/
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if ((info->samples == 8 && info->height > 4194304u) ||
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(info->samples == 4 && info->height > 8388608u))
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require_interleaved = true;
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/* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
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* Suface Storage Format:
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*
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* This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
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* one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
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* R24_UNORM_X8_TYPELESS.
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*/
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if (info->format == ISL_FORMAT_I24X8_UNORM ||
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info->format == ISL_FORMAT_L24X8_UNORM ||
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info->format == ISL_FORMAT_A24X8_UNORM ||
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info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
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require_interleaved = true;
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if (require_array && require_interleaved)
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return false;
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if (require_interleaved) {
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*msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
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return true;
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}
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/* Default to the array layout because it permits multisample
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* compression.
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*/
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*msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
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return true;
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}
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/**
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* @brief Filter out tiling flags that are incompatible with the surface.
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*
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* The resultant outgoing @a flags is a subset of the incoming @a flags. The
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* outgoing flags may be empty (0x0) if the incoming flags were too
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* restrictive.
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*
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* For example, if the surface will be used for a display
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* (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
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* flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
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*/
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void
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isl_gen6_filter_tiling(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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isl_tiling_flags_t *flags)
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{
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/* IVB+ requires separate stencil */
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assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
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/* Clear flags unsupported on this hardware */
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if (ISL_GFX_VER(dev) < 9) {
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*flags &= ~ISL_TILING_Yf_BIT;
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*flags &= ~ISL_TILING_Ys_BIT;
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}
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/* And... clear the Yf and Ys bits anyway because Anvil doesn't support
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* them yet.
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*/
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*flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */
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*flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */
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if (isl_surf_usage_is_depth(info->usage)) {
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/* Depth requires Y. */
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*flags &= ISL_TILING_ANY_Y_MASK;
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}
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if (isl_surf_usage_is_stencil(info->usage)) {
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if (ISL_GFX_VER(dev) >= 12) {
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/* Stencil requires Y. */
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*flags &= ISL_TILING_ANY_Y_MASK;
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} else {
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/* Stencil requires W. */
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*flags &= ISL_TILING_W_BIT;
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}
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} else {
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*flags &= ~ISL_TILING_W_BIT;
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}
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/* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
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* If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
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*/
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if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC)
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*flags &= ISL_TILING_Y0_BIT;
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/* MCS buffers are always Y-tiled */
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if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
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*flags &= ISL_TILING_Y0_BIT;
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if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
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ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
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ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
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assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
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isl_finishme("%s:%s: handle rotated display surfaces",
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__FILE__, __func__);
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}
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if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
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ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
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assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
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isl_finishme("%s:%s: handle flipped display surfaces",
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__FILE__, __func__);
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}
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if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
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if (ISL_GFX_VER(dev) >= 12) {
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*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
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ISL_TILING_Y0_BIT);
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} else if (ISL_GFX_VER(dev) >= 9) {
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/* Note we let Yf even though it was cleared above. This is just for
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* completeness.
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*/
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*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
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ISL_TILING_Y0_BIT | ISL_TILING_Yf_BIT);
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} else {
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/* Before Skylake, the display engine does not accept Y */
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*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
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}
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}
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if (info->samples > 1) {
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/* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
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* Surface:
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*
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* For multisample render targets, this field must be 1 (true). MSRTs
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* can only be tiled.
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*
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* From the Broadwell PRM >> Volume2d: Command Structures >>
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* RENDER_SURFACE_STATE Tile Mode:
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*
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* If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
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* must be YMAJOR.
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*
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* As usual, though, stencil is special and requires W-tiling.
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*/
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*flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
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}
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/* workaround */
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if (ISL_GFX_VER(dev) == 7 &&
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gen7_format_needs_valign2(dev, info->format) &&
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(info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
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info->samples == 1) {
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/* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
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* SURFACE_STATE Surface Vertical Alignment:
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*
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* This field must be set to VALIGN_4 for all tiled Y Render Target
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* surfaces.
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*/
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*flags &= ~ISL_TILING_Y0_BIT;
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}
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/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
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*
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* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
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* TileX or Linear."
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*
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* This is necessary all the way back to 965, but is permitted on Gen7+.
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*/
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if (ISL_GFX_VER(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
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*flags &= ~ISL_TILING_Y0_BIT;
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/* From the BDW and SKL PRMs, Volume 2d,
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* RENDER_SURFACE_STATE::Width - Programming Notes:
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*
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* A known issue exists if a primitive is rendered to the first 2 rows and
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* last 2 columns of a 16K width surface. If any geometry is drawn inside
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* this square it will be copied to column X=2 and X=3 (arrangement on Y
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* position will stay the same). If any geometry exceeds the boundaries of
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* this 2x2 region it will be drawn normally. The issue also only occurs
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* if the surface has TileMode != Linear.
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*
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* [Internal documentation notes that this issue isn't present on SKL GT4.]
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* To prevent this rendering corruption, only allow linear tiling for
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* surfaces with widths greater than 16K-2 pixels.
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*
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* TODO: Is this an issue for multisampled surfaces as well?
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*/
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if (info->width > 16382 && info->samples == 1 &&
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info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
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(ISL_GFX_VER(dev) == 8 ||
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(dev->info->is_skylake && dev->info->gt != 4))) {
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*flags &= ISL_TILING_LINEAR_BIT;
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}
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}
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void
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isl_gen7_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el)
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{
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assert(ISL_GFX_VER(dev) == 7);
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/* Handled by isl_choose_image_alignment_el */
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assert(info->format != ISL_FORMAT_HIZ);
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/* IVB+ does not support combined depthstencil. */
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assert(!isl_surf_usage_is_depth_and_stencil(info->usage));
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/* From the Ivy Bridge PRM, Vol. 2, Part 2, Section 6.18.4.4,
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* "Alignment unit size", the alignment parameters are summarized in the
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* following table:
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*
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* Surface Defined By | Surface Format | Align Width | Align Height
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* --------------------+-----------------+-------------+--------------
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* DEPTH_BUFFER | D16_UNORM | 8 | 4
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* | other | 4 | 4
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* --------------------+-----------------+-------------+--------------
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* STENCIL_BUFFER | N/A | 8 | 8
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* --------------------+-----------------+-------------+--------------
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* SURFACE_STATE | BC*, ETC*, EAC* | 4 | 4
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* | FXT1 | 8 | 4
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* | all others | HALIGN | VALIGN
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* -------------------------------------------------------------------
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*/
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if (isl_surf_usage_is_depth(info->usage)) {
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*image_align_el = info->format == ISL_FORMAT_R16_UNORM ?
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isl_extent3d(8, 4, 1) : isl_extent3d(4, 4, 1);
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return;
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} else if (isl_surf_usage_is_stencil(info->usage)) {
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*image_align_el = isl_extent3d(8, 8, 1);
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return;
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} else if (isl_format_is_compressed(info->format)) {
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/* Compressed formats all have alignment equal to block size. */
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*image_align_el = isl_extent3d(1, 1, 1);
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return;
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}
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/* Everything after this point is in the "set by Surface Horizontal or
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* Vertical Alignment" case. Now it's just a matter of applying
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* restrictions.
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*/
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/* There are no restrictions on halign beyond what's given in the table
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* above. We set it to the minimum value of 4 because that uses the least
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* memory.
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*/
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const uint32_t halign = 4;
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bool require_valign4 = false;
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/* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
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* RENDER_SURFACE_STATE Surface Vertical Alignment:
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*
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* * This field is intended to be set to VALIGN_4 if the surface was
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* rendered as a depth buffer,
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*
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* * for a multisampled (4x) render target, or for a multisampled (8x)
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* render target, since these surfaces support only alignment of 4.
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*
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* * This field must be set to VALIGN_4 for all tiled Y Render Target
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* surfaces
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*
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* * Value of 1 is not supported for format YCRCB_NORMAL (0x182),
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* YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
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*
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* * If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
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* must be set to VALIGN_4."
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*
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* The first restriction is already handled by the table above and the
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* second restriction is redundant with the fifth.
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*/
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if (info->samples > 1)
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require_valign4 = true;
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if (tiling == ISL_TILING_Y0 &&
|
||
(info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT))
|
||
require_valign4 = true;
|
||
|
||
assert(!(require_valign4 && gen7_format_needs_valign2(dev, info->format)));
|
||
|
||
/* We default to VALIGN_2 because it uses the least memory. */
|
||
const uint32_t valign = require_valign4 ? 4 : 2;
|
||
|
||
*image_align_el = isl_extent3d(halign, valign, 1);
|
||
}
|