742 lines
33 KiB
C
742 lines
33 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "gen8_pack.h"
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#include "gen9_pack.h"
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info)
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{
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const uint32_t num_dwords = 1 + info->attributeCount * 2;
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uint32_t *p;
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static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
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if (info->attributeCount > 0) {
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p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GENX(3DSTATE_VERTEX_ELEMENTS));
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}
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for (uint32_t i = 0; i < info->attributeCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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const struct anv_format *format = anv_format_for_vk_format(desc->format);
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struct GENX(VERTEX_ELEMENT_STATE) element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format->surface_format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offsetInBytes,
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.Component0Control = VFCOMP_STORE_SRC,
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.Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
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};
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GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
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.InstancingEnable = pipeline->instancing_enable[desc->binding],
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.VertexElementIndex = i,
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/* Vulkan so far doesn't have an instance divisor, so
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* this is always 1 (ignored if not instancing). */
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.InstanceDataStepRate = 1);
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}
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
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.VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
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.VertexIDComponentNumber = 2,
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.VertexIDElementOffset = info->bindingCount,
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.InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
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.InstanceIDComponentNumber = 3,
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.InstanceIDElementOffset = info->bindingCount);
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}
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static void
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emit_ia_state(struct anv_pipeline *pipeline,
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const VkPipelineInputAssemblyStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
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.PrimitiveTopologyType = pipeline->topology);
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}
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static void
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emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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static const uint32_t vk_to_gen_cullmode[] = {
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[VK_CULL_MODE_NONE] = CULLMODE_NONE,
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[VK_CULL_MODE_FRONT] = CULLMODE_FRONT,
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[VK_CULL_MODE_BACK] = CULLMODE_BACK,
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[VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
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};
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static const uint32_t vk_to_gen_fillmode[] = {
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[VK_FILL_MODE_POINTS] = RASTER_POINT,
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[VK_FILL_MODE_WIREFRAME] = RASTER_WIREFRAME,
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[VK_FILL_MODE_SOLID] = RASTER_SOLID
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};
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static const uint32_t vk_to_gen_front_face[] = {
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[VK_FRONT_FACE_CCW] = CounterClockwise,
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[VK_FRONT_FACE_CW] = Clockwise
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};
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.ViewportTransformEnable = !(extra && extra->disable_viewport),
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 0,
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.PointWidthSource = pipeline->writes_point_size ? Vertex : State,
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.PointWidth = 1.0,
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};
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/* FINISHME: VkBool32 rasterizerDiscardEnable; */
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GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
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struct GENX(3DSTATE_RASTER) raster = {
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GENX(3DSTATE_RASTER_header),
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.FrontWinding = vk_to_gen_front_face[info->frontFace],
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.CullMode = vk_to_gen_cullmode[info->cullMode],
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.FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode],
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.BackFaceFillMode = vk_to_gen_fillmode[info->fillMode],
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.ScissorRectangleEnable = !(extra && extra->disable_scissor),
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#if ANV_GEN == 8
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.ViewportZClipTestEnable = info->depthClipEnable
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#else
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/* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
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.ViewportZFarClipTestEnable = info->depthClipEnable,
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.ViewportZNearClipTestEnable = info->depthClipEnable,
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#endif
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};
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GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
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}
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static void
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emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info)
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{
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struct anv_device *device = pipeline->device;
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static const uint32_t vk_to_gen_logic_op[] = {
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[VK_LOGIC_OP_COPY] = LOGICOP_COPY,
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[VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
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[VK_LOGIC_OP_AND] = LOGICOP_AND,
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[VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
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[VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
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[VK_LOGIC_OP_NOOP] = LOGICOP_NOOP,
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[VK_LOGIC_OP_XOR] = LOGICOP_XOR,
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[VK_LOGIC_OP_OR] = LOGICOP_OR,
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[VK_LOGIC_OP_NOR] = LOGICOP_NOR,
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[VK_LOGIC_OP_EQUIV] = LOGICOP_EQUIV,
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[VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
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[VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
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[VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
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[VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
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[VK_LOGIC_OP_NAND] = LOGICOP_NAND,
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[VK_LOGIC_OP_SET] = LOGICOP_SET,
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};
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static const uint32_t vk_to_gen_blend[] = {
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[VK_BLEND_ZERO] = BLENDFACTOR_ZERO,
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[VK_BLEND_ONE] = BLENDFACTOR_ONE,
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[VK_BLEND_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
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[VK_BLEND_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
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[VK_BLEND_DEST_COLOR] = BLENDFACTOR_DST_COLOR,
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[VK_BLEND_ONE_MINUS_DEST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
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[VK_BLEND_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
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[VK_BLEND_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
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[VK_BLEND_DEST_ALPHA] = BLENDFACTOR_DST_ALPHA,
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[VK_BLEND_ONE_MINUS_DEST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
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[VK_BLEND_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
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[VK_BLEND_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR,
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[VK_BLEND_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
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[VK_BLEND_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA,
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[VK_BLEND_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
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[VK_BLEND_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
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[VK_BLEND_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
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[VK_BLEND_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
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[VK_BLEND_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
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};
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static const uint32_t vk_to_gen_blend_op[] = {
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[VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
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[VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
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[VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
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[VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
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[VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
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};
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uint32_t num_dwords = GENX(BLEND_STATE_length);
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToCoverageEnable = info->alphaToCoverageEnable,
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.AlphaToOneEnable = info->alphaToOneEnable,
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};
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for (uint32_t i = 0; i < info->attachmentCount; i++) {
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const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
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if (a->srcBlendColor != a->srcBlendAlpha ||
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a->destBlendColor != a->destBlendAlpha ||
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a->blendOpColor != a->blendOpAlpha) {
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blend_state.IndependentAlphaBlendEnable = true;
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}
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blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.PreBlendSourceOnlyClampEnable = false,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
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.DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
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.WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
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.WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
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.WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
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.WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
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};
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->blendOpColor == VK_BLEND_OP_MIN ||
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a->blendOpColor == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->blendOpAlpha == VK_BLEND_OP_MIN ||
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a->blendOpAlpha == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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}
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
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.BlendStatePointer = pipeline->blend_state.offset,
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.BlendStatePointerValid = true);
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}
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static const uint32_t vk_to_gen_compare_op[] = {
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[VK_COMPARE_OP_NEVER] = COMPAREFUNCTION_NEVER,
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[VK_COMPARE_OP_LESS] = COMPAREFUNCTION_LESS,
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[VK_COMPARE_OP_EQUAL] = COMPAREFUNCTION_EQUAL,
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[VK_COMPARE_OP_LESS_EQUAL] = COMPAREFUNCTION_LEQUAL,
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[VK_COMPARE_OP_GREATER] = COMPAREFUNCTION_GREATER,
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[VK_COMPARE_OP_NOT_EQUAL] = COMPAREFUNCTION_NOTEQUAL,
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[VK_COMPARE_OP_GREATER_EQUAL] = COMPAREFUNCTION_GEQUAL,
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[VK_COMPARE_OP_ALWAYS] = COMPAREFUNCTION_ALWAYS,
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};
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static const uint32_t vk_to_gen_stencil_op[] = {
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[VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
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[VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
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[VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
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[VK_STENCIL_OP_INC_CLAMP] = STENCILOP_INCRSAT,
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[VK_STENCIL_OP_DEC_CLAMP] = STENCILOP_DECRSAT,
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[VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
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[VK_STENCIL_OP_INC_WRAP] = STENCILOP_INCR,
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[VK_STENCIL_OP_DEC_WRAP] = STENCILOP_DECR,
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};
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static void
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emit_ds_state(struct anv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *info)
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{
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if (info == NULL) {
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/* We're going to OR this together with the dynamic state. We need
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* to make sure it's initialized to something useful.
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*/
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/* FIXME: gen9 wm_depth_stencil */
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memset(pipeline->gen8.wm_depth_stencil, 0,
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sizeof(pipeline->gen8.wm_depth_stencil));
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return;
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}
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/* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
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struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
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.DepthTestEnable = info->depthTestEnable,
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.DepthBufferWriteEnable = info->depthWriteEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DoubleSidedStencilEnable = true,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
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.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
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.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
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.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
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.BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
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.BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
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};
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GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, pipeline->gen8.wm_depth_stencil, &wm_depth_stencil);
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}
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VkResult
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genX(graphics_pipeline_create)(
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VkDevice _device,
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const VkGraphicsPipelineCreateInfo* pCreateInfo,
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const struct anv_graphics_pipeline_create_info *extra,
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_pipeline *pipeline;
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VkResult result;
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uint32_t offset, length;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
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pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
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VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
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if (pipeline == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
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if (result != VK_SUCCESS)
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return result;
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/* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
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* hard code this to num_attributes - 2. This is because the attributes
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* include VUE header and position, which aren't counted as varying
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* inputs. */
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if (pipeline->vs_simd8 == NO_KERNEL) {
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pipeline->wm_prog_data.num_varying_inputs =
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pCreateInfo->pVertexInputState->attributeCount - 2;
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}
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assert(pCreateInfo->pVertexInputState);
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emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
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assert(pCreateInfo->pInputAssemblyState);
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emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
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assert(pCreateInfo->pRasterState);
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emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS),
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.StatisticsEnable = true);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), .Enable = false);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), .TEEnable = false);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), .FunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
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.ConstantBufferOffset = 0,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS),
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.ConstantBufferOffset = 4,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS),
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.ConstantBufferOffset = 8,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM_CHROMAKEY),
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.ChromaKeyKillEnable = false);
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
|
|
.ClipEnable = true,
|
|
.ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
|
|
.MinimumPointWidth = 0.125,
|
|
.MaximumPointWidth = 255.875);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
|
|
.StatisticsEnable = true,
|
|
.LineEndCapAntialiasingRegionWidth = _05pixels,
|
|
.LineAntialiasingRegionWidth = _10pixels,
|
|
.EarlyDepthStencilControl = NORMAL,
|
|
.ForceThreadDispatchEnable = NORMAL,
|
|
.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
|
|
.BarycentricInterpolationMode =
|
|
pipeline->wm_prog_data.barycentric_interp_modes);
|
|
|
|
uint32_t samples = 1;
|
|
uint32_t log2_samples = __builtin_ffs(samples) - 1;
|
|
bool enable_sampling = samples > 1 ? true : false;
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
|
|
.PixelPositionOffsetEnable = enable_sampling,
|
|
.PixelLocation = CENTER,
|
|
.NumberofMultisamples = log2_samples);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
|
|
.SampleMask = 0xffff);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
|
|
.VSURBStartingAddress = pipeline->urb.vs_start,
|
|
.VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
|
|
.VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS),
|
|
.GSURBStartingAddress = pipeline->urb.gs_start,
|
|
.GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
|
|
.GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS),
|
|
.HSURBStartingAddress = pipeline->urb.vs_start,
|
|
.HSURBEntryAllocationSize = 0,
|
|
.HSNumberofURBEntries = 0);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS),
|
|
.DSURBStartingAddress = pipeline->urb.vs_start,
|
|
.DSURBEntryAllocationSize = 0,
|
|
.DSNumberofURBEntries = 0);
|
|
|
|
const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
|
|
offset = 1;
|
|
length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
|
|
|
|
if (pipeline->gs_vec4 == NO_KERNEL)
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
|
|
else
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
|
|
.SingleProgramFlow = false,
|
|
.KernelStartPointer = pipeline->gs_vec4,
|
|
.VectorMaskEnable = Dmask,
|
|
.SamplerCount = 0,
|
|
.BindingTableEntryCount = 0,
|
|
.ExpectedVertexCount = pipeline->gs_vertex_count,
|
|
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
|
|
.PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
|
|
|
|
.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
|
|
.OutputTopology = gs_prog_data->output_topology,
|
|
.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
|
|
.DispatchGRFStartRegisterForURBData =
|
|
gs_prog_data->base.base.dispatch_grf_start_reg,
|
|
|
|
.MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
|
|
.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
|
|
.DispatchMode = gs_prog_data->base.dispatch_mode,
|
|
.StatisticsEnable = true,
|
|
.IncludePrimitiveID = gs_prog_data->include_primitive_id,
|
|
.ReorderMode = TRAILING,
|
|
.Enable = true,
|
|
|
|
.ControlDataFormat = gs_prog_data->control_data_format,
|
|
|
|
.StaticOutput = gs_prog_data->static_vertex_count >= 0,
|
|
.StaticOutputVertexCount =
|
|
gs_prog_data->static_vertex_count >= 0 ?
|
|
gs_prog_data->static_vertex_count : 0,
|
|
|
|
/* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
|
|
* UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
|
|
* UserClipDistanceCullTestEnableBitmask(v)
|
|
*/
|
|
|
|
.VertexURBEntryOutputReadOffset = offset,
|
|
.VertexURBEntryOutputLength = length);
|
|
|
|
const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
|
|
/* Skip the VUE header and position slots */
|
|
offset = 1;
|
|
length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
|
|
|
|
if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
|
|
.FunctionEnable = false,
|
|
/* Even if VS is disabled, SBE still gets the amount of
|
|
* vertex data to read from this field. */
|
|
.VertexURBEntryOutputReadOffset = offset,
|
|
.VertexURBEntryOutputLength = length);
|
|
else
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
|
|
.KernelStartPointer = pipeline->vs_simd8,
|
|
.SingleVertexDispatch = Multiple,
|
|
.VectorMaskEnable = Dmask,
|
|
.SamplerCount = 0,
|
|
.BindingTableEntryCount =
|
|
vue_prog_data->base.binding_table.size_bytes / 4,
|
|
.ThreadDispatchPriority = Normal,
|
|
.FloatingPointMode = IEEE754,
|
|
.IllegalOpcodeExceptionEnable = false,
|
|
.AccessesUAV = false,
|
|
.SoftwareExceptionEnable = false,
|
|
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
|
|
.PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
|
|
|
|
.DispatchGRFStartRegisterForURBData =
|
|
vue_prog_data->base.dispatch_grf_start_reg,
|
|
.VertexURBEntryReadLength = vue_prog_data->urb_read_length,
|
|
.VertexURBEntryReadOffset = 0,
|
|
|
|
.MaximumNumberofThreads = device->info.max_vs_threads - 1,
|
|
.StatisticsEnable = false,
|
|
.SIMD8DispatchEnable = true,
|
|
.VertexCacheDisable = false,
|
|
.FunctionEnable = true,
|
|
|
|
.VertexURBEntryOutputReadOffset = offset,
|
|
.VertexURBEntryOutputLength = length,
|
|
.UserClipDistanceClipTestEnableBitmask = 0,
|
|
.UserClipDistanceCullTestEnableBitmask = 0);
|
|
|
|
const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
|
|
|
|
/* TODO: We should clean this up. Among other things, this is mostly
|
|
* shared with other gens.
|
|
*/
|
|
const struct brw_vue_map *fs_input_map;
|
|
if (pipeline->gs_vec4 == NO_KERNEL)
|
|
fs_input_map = &vue_prog_data->vue_map;
|
|
else
|
|
fs_input_map = &gs_prog_data->base.vue_map;
|
|
|
|
struct GENX(3DSTATE_SBE_SWIZ) swiz = {
|
|
GENX(3DSTATE_SBE_SWIZ_header),
|
|
};
|
|
|
|
int max_source_attr = 0;
|
|
for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
|
|
int input_index = wm_prog_data->urb_setup[attr];
|
|
|
|
if (input_index < 0)
|
|
continue;
|
|
|
|
/* We have to subtract two slots to accout for the URB entry output
|
|
* read offset in the VS and GS stages.
|
|
*/
|
|
int source_attr = fs_input_map->varying_to_slot[attr] - 2;
|
|
max_source_attr = MAX2(max_source_attr, source_attr);
|
|
|
|
if (input_index >= 16)
|
|
continue;
|
|
|
|
swiz.Attribute[input_index].SourceAttribute = source_attr;
|
|
}
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
|
|
.AttributeSwizzleEnable = true,
|
|
.ForceVertexURBEntryReadLength = false,
|
|
.ForceVertexURBEntryReadOffset = false,
|
|
.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2),
|
|
.PointSpriteTextureCoordinateOrigin = UPPERLEFT,
|
|
.NumberofSFOutputAttributes =
|
|
wm_prog_data->num_varying_inputs,
|
|
|
|
#if ANV_GEN >= 9
|
|
.Attribute0ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute1ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute2ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute3ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute4ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute5ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute6ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute7ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute8ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute9ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute10ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute11ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute12ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute13ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute14ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute15ActiveComponentFormat = ACF_XYZW,
|
|
/* wow, much field, very attribute */
|
|
.Attribute16ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute17ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute18ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute19ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute20ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute21ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute22ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute23ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute24ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute25ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute26ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute27ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute28ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute29ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute28ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute29ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute30ActiveComponentFormat = ACF_XYZW,
|
|
#endif
|
|
);
|
|
|
|
uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
|
|
GENX(3DSTATE_SBE_SWIZ_length));
|
|
GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
|
|
|
|
const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
|
|
.KernelStartPointer0 = pipeline->ps_ksp0,
|
|
|
|
.SingleProgramFlow = false,
|
|
.VectorMaskEnable = true,
|
|
.SamplerCount = 1,
|
|
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
|
|
.PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
|
|
|
|
.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
|
|
.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
|
|
POSOFFSET_SAMPLE: POSOFFSET_NONE,
|
|
.PushConstantEnable = wm_prog_data->base.nr_params > 0,
|
|
._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
|
|
._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
|
|
._32PixelDispatchEnable = false,
|
|
|
|
.DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
|
|
.DispatchGRFStartRegisterForConstantSetupData1 = 0,
|
|
.DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
|
|
|
|
.KernelStartPointer1 = 0,
|
|
.KernelStartPointer2 = pipeline->ps_ksp2);
|
|
|
|
bool per_sample_ps = false;
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
|
|
.PixelShaderValid = true,
|
|
.PixelShaderKillsPixel = wm_prog_data->uses_kill,
|
|
.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
|
|
.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
|
|
.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
|
|
.PixelShaderIsPerSample = per_sample_ps,
|
|
#if ANV_GEN >= 9
|
|
.PixelShaderPullsBary = wm_prog_data->pulls_bary,
|
|
.InputCoverageMaskState = ICMS_NONE
|
|
#endif
|
|
);
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
VkResult genX(compute_pipeline_create)(
|
|
VkDevice _device,
|
|
const VkComputePipelineCreateInfo* pCreateInfo,
|
|
VkPipeline* pPipeline)
|
|
{
|
|
ANV_FROM_HANDLE(anv_device, device, _device);
|
|
struct anv_pipeline *pipeline;
|
|
VkResult result;
|
|
|
|
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
|
|
|
|
pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
|
|
VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
|
|
if (pipeline == NULL)
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
pipeline->device = device;
|
|
pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
|
|
|
|
pipeline->blend_state.map = NULL;
|
|
|
|
result = anv_reloc_list_init(&pipeline->batch_relocs, device);
|
|
if (result != VK_SUCCESS) {
|
|
anv_device_free(device, pipeline);
|
|
return result;
|
|
}
|
|
pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
|
|
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
|
|
pipeline->batch.relocs = &pipeline->batch_relocs;
|
|
|
|
anv_state_stream_init(&pipeline->program_stream,
|
|
&device->instruction_block_pool);
|
|
|
|
/* When we free the pipeline, we detect stages based on the NULL status
|
|
* of various prog_data pointers. Make them NULL by default.
|
|
*/
|
|
memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
|
|
memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
|
|
|
|
pipeline->vs_simd8 = NO_KERNEL;
|
|
pipeline->vs_vec4 = NO_KERNEL;
|
|
pipeline->gs_vec4 = NO_KERNEL;
|
|
|
|
pipeline->active_stages = 0;
|
|
pipeline->total_scratch = 0;
|
|
|
|
assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE);
|
|
ANV_FROM_HANDLE(anv_shader, shader, pCreateInfo->stage.shader);
|
|
anv_pipeline_compile_cs(pipeline, pCreateInfo, shader);
|
|
|
|
pipeline->use_repclear = false;
|
|
|
|
const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_COMPUTE],
|
|
.PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
|
|
.ScratchSpaceBasePointerHigh = 0,
|
|
.StackSize = 0,
|
|
|
|
.MaximumNumberofThreads = device->info.max_cs_threads - 1,
|
|
.NumberofURBEntries = 2,
|
|
.ResetGatewayTimer = true,
|
|
#if ANV_GEN == 8
|
|
.BypassGatewayControl = true,
|
|
#endif
|
|
.URBEntryAllocationSize = 2,
|
|
.CURBEAllocationSize = 0);
|
|
|
|
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
|
|
uint32_t group_size = prog_data->local_size[0] *
|
|
prog_data->local_size[1] * prog_data->local_size[2];
|
|
pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
|
|
uint32_t remainder = group_size & (prog_data->simd_size - 1);
|
|
|
|
if (remainder > 0)
|
|
pipeline->cs_right_mask = ~0u >> (32 - remainder);
|
|
else
|
|
pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
|
|
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|