cd39d3b1ad
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "gen_device" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen_device/intel_device}"' \;
grep -E "gen_device_info*\.[cph]" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device_info\(.*\.[cph]\)/intel_device_info\1/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
110 lines
3.6 KiB
C
110 lines
3.6 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef INTEL_L3_CONFIG_H
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#define INTEL_L3_CONFIG_H
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#include <stdio.h>
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#include "dev/intel_device_info.h"
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/**
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* Chunk of L3 cache reserved for some specific purpose.
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*/
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enum intel_l3_partition {
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/** Shared local memory. */
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INTEL_L3P_SLM = 0,
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/** Unified return buffer. */
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INTEL_L3P_URB,
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/** Union of DC and RO. */
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INTEL_L3P_ALL,
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/** Data cluster RW partition. */
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INTEL_L3P_DC,
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/** Union of IS, C and T. */
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INTEL_L3P_RO,
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/** Instruction and state cache. */
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INTEL_L3P_IS,
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/** Constant cache. */
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INTEL_L3P_C,
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/** Texture cache. */
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INTEL_L3P_T,
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/** Number of supported L3 partitions. */
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INTEL_NUM_L3P
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};
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/**
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* L3 configuration represented as the number of ways allocated for each
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* partition. \sa get_l3_way_size().
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*/
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struct intel_l3_config {
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unsigned n[INTEL_NUM_L3P];
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};
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/**
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* L3 configuration represented as a vector of weights giving the desired
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* relative size of each partition. The scale is arbitrary, only the ratios
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* between weights will have an influence on the selection of the closest L3
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* configuration.
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*/
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struct intel_l3_weights {
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float w[INTEL_NUM_L3P];
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};
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float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1);
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struct intel_l3_weights
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intel_get_default_l3_weights(const struct gen_device_info *devinfo,
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bool needs_dc, bool needs_slm);
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struct intel_l3_weights
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intel_get_l3_config_weights(const struct intel_l3_config *cfg);
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const struct intel_l3_config *
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intel_get_default_l3_config(const struct gen_device_info *devinfo);
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const struct intel_l3_config *
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intel_get_l3_config(const struct gen_device_info *devinfo,
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struct intel_l3_weights w0);
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unsigned
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intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
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const struct intel_l3_config *cfg);
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void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
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enum intel_urb_deref_block_size {
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INTEL_URB_DEREF_BLOCK_SIZE_32 = 0,
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INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY = 1,
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INTEL_URB_DEREF_BLOCK_SIZE_8 = 2,
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};
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void intel_get_urb_config(const struct gen_device_info *devinfo,
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const struct intel_l3_config *l3_cfg,
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bool tess_present, bool gs_present,
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const unsigned entry_size[4],
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unsigned entries[4], unsigned start[4],
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enum intel_urb_deref_block_size *deref_block_size,
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bool *constrained);
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#endif /* INTEL_L3_CONFIG_H */
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