362 lines
15 KiB
C
362 lines
15 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef IRIS_CONTEXT_H
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#define IRIS_CONTEXT_H
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#include "pipe/p_context.h"
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#include "pipe/p_state.h"
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#include "util/u_debug.h"
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#include "intel/common/gen_debug.h"
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#include "intel/compiler/brw_compiler.h"
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#include "iris_batch.h"
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#include "iris_binder.h"
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#include "iris_screen.h"
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struct iris_bo;
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struct iris_context;
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struct blorp_batch;
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struct blorp_params;
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#define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
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#define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
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#define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
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#define IRIS_MAX_TEXTURE_SAMPLERS 32
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#define IRIS_MAX_VIEWPORTS 16
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#define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0)
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#define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1)
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#define IRIS_DIRTY_SCISSOR_RECT (1ull << 2)
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#define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3)
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#define IRIS_DIRTY_CC_VIEWPORT (1ull << 4)
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#define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5)
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#define IRIS_DIRTY_PS_BLEND (1ull << 6)
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#define IRIS_DIRTY_BLEND_STATE (1ull << 7)
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#define IRIS_DIRTY_RASTER (1ull << 8)
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#define IRIS_DIRTY_CLIP (1ull << 9)
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#define IRIS_DIRTY_SCISSOR (1ull << 10)
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#define IRIS_DIRTY_LINE_STIPPLE (1ull << 11)
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#define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12)
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#define IRIS_DIRTY_MULTISAMPLE (1ull << 13)
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#define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14)
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#define IRIS_DIRTY_SAMPLE_MASK (1ull << 15)
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#define IRIS_DIRTY_SAMPLER_STATES_VS (1ull << 16)
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#define IRIS_DIRTY_SAMPLER_STATES_TCS (1ull << 17)
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#define IRIS_DIRTY_SAMPLER_STATES_TES (1ull << 18)
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#define IRIS_DIRTY_SAMPLER_STATES_GS (1ull << 19)
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#define IRIS_DIRTY_SAMPLER_STATES_PS (1ull << 20)
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#define IRIS_DIRTY_SAMPLER_STATES_CS (1ull << 21)
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#define IRIS_DIRTY_UNCOMPILED_VS (1ull << 22)
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#define IRIS_DIRTY_UNCOMPILED_TCS (1ull << 23)
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#define IRIS_DIRTY_UNCOMPILED_TES (1ull << 24)
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#define IRIS_DIRTY_UNCOMPILED_GS (1ull << 25)
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#define IRIS_DIRTY_UNCOMPILED_FS (1ull << 26)
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#define IRIS_DIRTY_UNCOMPILED_CS (1ull << 27)
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#define IRIS_DIRTY_VS (1ull << 28)
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#define IRIS_DIRTY_TCS (1ull << 29)
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#define IRIS_DIRTY_TES (1ull << 30)
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#define IRIS_DIRTY_GS (1ull << 31)
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#define IRIS_DIRTY_FS (1ull << 32)
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#define IRIS_DIRTY_CS (1ull << 33)
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#define IRIS_DIRTY_URB (1ull << 34)
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#define IRIS_DIRTY_CONSTANTS_VS (1ull << 35)
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#define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36)
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#define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
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#define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
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#define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
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enum brw_param_domain {
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BRW_PARAM_DOMAIN_BUILTIN = 0,
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BRW_PARAM_DOMAIN_PARAMETER,
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BRW_PARAM_DOMAIN_UNIFORM,
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BRW_PARAM_DOMAIN_IMAGE,
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};
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#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
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#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
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#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
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#define BRW_PARAM_PARAMETER(idx, comp) \
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BRW_PARAM(PARAMETER, ((idx) << 2) | (comp))
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#define BRW_PARAM_PARAMETER_IDX(param) (BRW_PARAM_VALUE(param) >> 2)
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#define BRW_PARAM_PARAMETER_COMP(param) (BRW_PARAM_VALUE(param) & 0x3)
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#define BRW_PARAM_UNIFORM(idx) BRW_PARAM(UNIFORM, (idx))
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#define BRW_PARAM_UNIFORM_IDX(param) BRW_PARAM_VALUE(param)
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#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
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#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
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#define BRW_PARAM_IMAGE_OFFSET(value) (BRW_PARAM_VALUE(value) & 0xf)
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struct iris_depth_stencil_alpha_state;
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enum iris_program_cache_id {
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IRIS_CACHE_VS = MESA_SHADER_VERTEX,
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IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
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IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
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IRIS_CACHE_GS = MESA_SHADER_GEOMETRY,
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IRIS_CACHE_FS = MESA_SHADER_FRAGMENT,
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IRIS_CACHE_CS = MESA_SHADER_COMPUTE,
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IRIS_CACHE_BLORP_BLIT,
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};
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/** @{
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*
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* PIPE_CONTROL operation, a combination MI_FLUSH and register write with
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* additional flushing control.
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*
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* The bits here are not the actual hardware values. The actual values
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* shift around a bit per-generation, so we just have flags for each
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* potential operation, and use genxml to encode the actual packet.
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*/
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enum pipe_control_flags
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{
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PIPE_CONTROL_FLUSH_LLC = (1 << 1),
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PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2),
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PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3),
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PIPE_CONTROL_CS_STALL = (1 << 4),
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PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5),
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PIPE_CONTROL_SYNC_GFDT = (1 << 6),
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PIPE_CONTROL_TLB_INVALIDATE = (1 << 7),
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PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8),
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PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9),
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PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10),
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PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11),
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PIPE_CONTROL_DEPTH_STALL = (1 << 12),
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PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
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PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14),
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15),
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PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
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PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17),
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PIPE_CONTROL_FLUSH_ENABLE = (1 << 18),
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PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19),
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PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20),
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PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21),
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PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22),
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PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23),
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PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24),
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};
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#define PIPE_CONTROL_CACHE_FLUSH_BITS \
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(PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
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PIPE_CONTROL_DATA_CACHE_FLUSH | \
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PIPE_CONTROL_RENDER_TARGET_FLUSH)
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#define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
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(PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
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PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
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PIPE_CONTROL_VF_CACHE_INVALIDATE | \
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
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PIPE_CONTROL_INSTRUCTION_INVALIDATE)
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/** @} */
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struct iris_compiled_shader {
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/** Buffer containing the uploaded assembly. */
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struct pipe_resource *buffer;
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/** Offset where the assembly lives in the BO. */
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unsigned offset;
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/** Pointer to the assembly in the BO's map. */
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void *map;
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/** The program data (owned by the program cache hash table) */
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struct brw_stage_prog_data *prog_data;
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/**
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* Shader packets and other data derived from prog_data. These must be
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* completely determined from prog_data.
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*/
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uint8_t derived_data[0];
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};
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struct iris_shader_state {
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struct pipe_constant_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
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struct pipe_resource *push_resource;
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unsigned const_offset;
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unsigned const_size;
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};
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struct iris_vtable {
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void (*destroy_state)(struct iris_context *ice);
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void (*init_render_context)(struct iris_screen *screen,
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struct iris_batch *batch,
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struct iris_vtable *vtbl,
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struct pipe_debug_callback *dbg);
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void (*upload_render_state)(struct iris_context *ice,
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struct iris_batch *batch,
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const struct pipe_draw_info *draw);
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void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
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struct iris_bo *bo, uint32_t offset,
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uint64_t imm);
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void (*blorp_exec)(struct blorp_batch *blorp_batch,
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const struct blorp_params *params);
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unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
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void (*set_derived_program_state)(const struct gen_device_info *devinfo,
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enum iris_program_cache_id cache_id,
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struct iris_compiled_shader *shader);
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void (*populate_vs_key)(const struct iris_context *ice,
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struct brw_vs_prog_key *key);
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void (*populate_tcs_key)(const struct iris_context *ice,
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struct brw_tcs_prog_key *key);
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void (*populate_tes_key)(const struct iris_context *ice,
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struct brw_tes_prog_key *key);
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void (*populate_gs_key)(const struct iris_context *ice,
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struct brw_gs_prog_key *key);
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void (*populate_fs_key)(const struct iris_context *ice,
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struct brw_wm_prog_key *key);
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};
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struct iris_context {
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struct pipe_context ctx;
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struct pipe_debug_callback dbg;
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struct iris_vtable vtbl;
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struct {
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struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
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struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
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struct brw_vue_map *last_vue_map;
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struct iris_shader_state state[MESA_SHADER_STAGES];
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struct u_upload_mgr *uploader;
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struct hash_table *cache;
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unsigned urb_size;
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} shaders;
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/** The main batch for rendering */
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struct iris_batch render_batch;
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struct {
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uint64_t dirty;
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unsigned num_viewports; // XXX: can viewports + scissors be different?
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unsigned num_scissors;
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unsigned sample_mask;
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struct iris_blend_state *cso_blend;
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struct iris_rasterizer_state *cso_rast;
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struct iris_depth_stencil_alpha_state *cso_zsa;
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struct iris_vertex_element_state *cso_vertex_elements;
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struct iris_vertex_buffer_state *cso_vertex_buffers;
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struct iris_viewport_state *cso_vp;
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struct iris_depth_state *cso_depth;
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struct pipe_blend_color blend_color;
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struct pipe_poly_stipple poly_stipple;
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struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
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struct pipe_stencil_ref stencil_ref;
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struct pipe_framebuffer_state framebuffer;
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struct pipe_resource *sampler_table_resource[MESA_SHADER_STAGES];
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uint32_t sampler_table_offset[MESA_SHADER_STAGES];
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struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
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struct iris_sampler_view *textures[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS];
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unsigned num_samplers[MESA_SHADER_STAGES];
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unsigned num_textures[MESA_SHADER_STAGES];
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struct iris_binder binder;
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struct u_upload_mgr *surface_uploader;
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// XXX: may want a separate uploader for "hey I made a CSO!" vs
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// "I'm streaming this out at draw time and never want it again!"
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struct u_upload_mgr *dynamic_uploader;
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} state;
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};
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#define perf_debug(dbg, ...) do { \
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if (INTEL_DEBUG & DEBUG_PERF) \
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dbg_printf(__VA_ARGS__); \
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if (unlikely(dbg)) \
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pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
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} while(0)
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double get_time(void);
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struct pipe_context *
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iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
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void iris_init_blit_functions(struct pipe_context *ctx);
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void iris_init_clear_functions(struct pipe_context *ctx);
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void iris_init_program_functions(struct pipe_context *ctx);
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void iris_init_resource_functions(struct pipe_context *ctx);
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void iris_init_query_functions(struct pipe_context *ctx);
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void iris_update_compiled_shaders(struct iris_context *ice);
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/* iris_draw.c */
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void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
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/* iris_pipe_control.c */
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void iris_emit_pipe_control_flush(struct iris_batch *batch,
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uint32_t flags);
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void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
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struct iris_bo *bo, uint32_t offset,
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uint64_t imm);
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void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
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uint32_t flags);
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void iris_cache_sets_clear(struct iris_batch *batch);
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void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
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void iris_cache_flush_for_render(struct iris_batch *batch,
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struct iris_bo *bo,
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enum isl_format format,
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enum isl_aux_usage aux_usage);
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void iris_render_cache_add_bo(struct iris_batch *batch,
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struct iris_bo *bo,
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enum isl_format format,
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enum isl_aux_usage aux_usage);
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void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
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void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
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/* iris_blorp.c */
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void gen9_init_blorp(struct iris_context *ice);
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void gen10_init_blorp(struct iris_context *ice);
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/* iris_state.c */
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void gen9_init_state(struct iris_context *ice);
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void gen10_init_state(struct iris_context *ice);
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/* iris_program_cache.c */
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void iris_init_program_cache(struct iris_context *ice);
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void iris_destroy_program_cache(struct iris_context *ice);
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void iris_print_program_cache(struct iris_context *ice);
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bool iris_bind_cached_shader(struct iris_context *ice,
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enum iris_program_cache_id cache_id,
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const void *key);
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void iris_upload_and_bind_shader(struct iris_context *ice,
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enum iris_program_cache_id cache_id,
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const void *key,
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const void *assembly,
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struct brw_stage_prog_data *prog_data);
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const void *iris_find_previous_compile(const struct iris_context *ice,
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enum iris_program_cache_id cache_id,
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unsigned program_string_id);
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#endif
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