c27fcb1d3b
We'd like to add safeguards against accidental use of MOCS 0 (uncached), which can have large performance implications. One case where we use MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS really shouldn't matter, as there's no actual surface to be cached. That said, it should be harmless to set MOCS for these null surfaces. We now set the one provided in info->mocs regardless of whether any buffers actually exist or not. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
334 lines
12 KiB
C
334 lines
12 KiB
C
/*
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* Copyright 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdint.h>
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#define __gen_address_type uint64_t
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#define __gen_user_data void
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static uint64_t
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__gen_combine_address(__attribute__((unused)) void *data,
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__attribute__((unused)) void *loc, uint64_t addr,
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uint32_t delta)
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{
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return addr + delta;
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}
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "isl_priv.h"
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static const uint32_t isl_encode_ds_surftype[] = {
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#if GFX_VER >= 9
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/* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
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*
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* "If depth/stencil is enabled with 1D render target, depth/stencil
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* surface type needs to be set to 2D surface type and height set to 1.
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* Depth will use (legacy) TileY and stencil will use TileW. For this
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* case only, the Surface Type of the depth buffer can be 2D while the
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* Surface Type of the render target(s) are 1D, representing an
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* exception to a programming note above.
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*/
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[ISL_SURF_DIM_1D] = SURFTYPE_2D,
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#else
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[ISL_SURF_DIM_1D] = SURFTYPE_1D,
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#endif
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[ISL_SURF_DIM_2D] = SURFTYPE_2D,
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[ISL_SURF_DIM_3D] = SURFTYPE_3D,
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};
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#if GFX_VERx10 >= 125
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static const uint8_t isl_encode_tiling[] = {
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[ISL_TILING_4] = TILE4,
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[ISL_TILING_64] = TILE64,
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};
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#endif
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void
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isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
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const struct isl_depth_stencil_hiz_emit_info *restrict info)
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{
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struct GENX(3DSTATE_DEPTH_BUFFER) db = {
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GENX(3DSTATE_DEPTH_BUFFER_header),
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#if GFX_VER >= 6
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.MOCS = info->mocs,
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#endif
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};
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if (info->depth_surf) {
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db.SurfaceType = isl_encode_ds_surftype[info->depth_surf->dim];
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db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
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db.Width = info->depth_surf->logical_level0_px.width - 1;
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db.Height = info->depth_surf->logical_level0_px.height - 1;
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if (db.SurfaceType == SURFTYPE_3D)
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db.Depth = info->depth_surf->logical_level0_px.depth - 1;
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} else if (info->stencil_surf) {
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db.SurfaceType = isl_encode_ds_surftype[info->stencil_surf->dim];
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db.SurfaceFormat = D32_FLOAT;
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db.Width = info->stencil_surf->logical_level0_px.width - 1;
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db.Height = info->stencil_surf->logical_level0_px.height - 1;
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if (db.SurfaceType == SURFTYPE_3D)
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db.Depth = info->stencil_surf->logical_level0_px.depth - 1;
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} else {
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db.SurfaceType = SURFTYPE_NULL;
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db.SurfaceFormat = D32_FLOAT;
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}
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if (info->depth_surf || info->stencil_surf) {
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/* These are based entirely on the view */
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db.RenderTargetViewExtent = info->view->array_len - 1;
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db.LOD = info->view->base_level;
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db.MinimumArrayElement = info->view->base_array_layer;
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/* From the Haswell PRM docs for 3DSTATE_DEPTH_BUFFER::Depth
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*
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* "This field specifies the total number of levels for a volume
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* texture or the number of array elements allowed to be accessed
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* starting at the Minimum Array Element for arrayed surfaces. If the
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* volume texture is MIP-mapped, this field specifies the depth of
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* the base MIP level."
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*
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* For 3D surfaces, we set it to the correct depth above. For non-3D
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* surfaces, this is the same as RenderTargetViewExtent.
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*/
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if (db.SurfaceType != SURFTYPE_3D)
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db.Depth = db.RenderTargetViewExtent;
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}
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if (info->depth_surf) {
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#if GFX_VER >= 7
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db.DepthWriteEnable = true;
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#endif
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db.SurfaceBaseAddress = info->depth_address;
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#if GFX_VERx10 >= 125
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db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
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db.MipTailStartLOD = 15;
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db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
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db.RenderCompressionFormat =
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isl_get_render_compression_format(info->depth_surf->format);
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#elif GFX_VER <= 6
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db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
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db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
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TILEWALK_XMAJOR;
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db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
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#endif
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db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
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#if GFX_VER >= 8
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db.SurfaceQPitch =
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isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
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#endif
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#if GFX_VER >= 12
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db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
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isl_aux_usage_has_ccs(info->hiz_usage);
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#endif
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}
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#if GFX_VER == 5 || GFX_VER == 6
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const bool separate_stencil =
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info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
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if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
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assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
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db.SeparateStencilBufferEnable = true;
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db.HierarchicalDepthBufferEnable = true;
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}
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#endif
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#if GFX_VER >= 6
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struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
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GENX(3DSTATE_STENCIL_BUFFER_header),
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sb.MOCS = info->mocs,
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};
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#else
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# define sb db
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#endif
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if (info->stencil_surf) {
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#if GFX_VER >= 7 && GFX_VER < 12
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db.StencilWriteEnable = true;
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#endif
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#if GFX_VERx10 >= 125
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sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
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sb.MipTailStartLOD = 15;
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sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
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sb.RenderCompressionFormat =
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isl_get_render_compression_format(info->stencil_surf->format);
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#endif
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#if GFX_VER >= 12
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sb.StencilWriteEnable = true;
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sb.SurfaceType = SURFTYPE_2D;
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sb.Width = info->stencil_surf->logical_level0_px.width - 1;
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sb.Height = info->stencil_surf->logical_level0_px.height - 1;
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sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
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sb.SurfLOD = info->view->base_level;
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sb.MinimumArrayElement = info->view->base_array_layer;
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assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
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info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
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sb.StencilCompressionEnable =
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info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
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sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
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#elif GFX_VERx10 >= 75
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sb.StencilBufferEnable = true;
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#endif
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sb.SurfaceBaseAddress = info->stencil_address;
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sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
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#if GFX_VER >= 8
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sb.SurfaceQPitch =
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isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
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#endif
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} else {
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#if GFX_VER >= 12
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sb.SurfaceType = SURFTYPE_NULL;
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/* The docs seem to indicate that if surf-type is null, then we may need
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* to match the depth-buffer value for `Depth`. It may be a
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* documentation bug, since the other fields don't require this.
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*
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* TODO: Confirm documentation and remove seeting of `Depth` if not
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* required.
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*/
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sb.Depth = db.Depth;
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#endif
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}
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#if GFX_VER >= 6
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struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
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GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
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.MOCS = info->mocs,
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};
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struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
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GENX(3DSTATE_CLEAR_PARAMS_header),
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};
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assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
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isl_aux_usage_has_hiz(info->hiz_usage));
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if (isl_aux_usage_has_hiz(info->hiz_usage)) {
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assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
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db.HierarchicalDepthBufferEnable = true;
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hiz.SurfaceBaseAddress = info->hiz_address;
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hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
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#if GFX_VERx10 >= 125
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hiz.TiledMode = isl_encode_tiling[info->hiz_surf->tiling];
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#endif
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#if GFX_VER >= 12
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hiz.HierarchicalDepthBufferWriteThruEnable =
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info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
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/* The bspec docs for this bit are fairly unclear about exactly what is
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* and isn't supported with HiZ write-through. It's fairly clear that
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* you can't sample from a multisampled depth buffer with CCS. This
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* limitation isn't called out explicitly but the docs for the CCS_E
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* value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
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*
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* "If Number of multisamples > 1, programming this value means MSAA
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* compression is enabled for that surface. Auxillary surface is MSC
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* with tile y."
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*
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* Since this interpretation ignores whether the surface is
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* depth/stencil or not and since multisampled depth buffers use
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* ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
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* compression, this means that we can't even specify MSAA depth CCS in
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* RENDER_SURFACE_STATE::AuxiliarySurfaceMode. The BSpec also says, for
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* 3DSTATE_HIER_DEPTH_BUFFER::HierarchicalDepthBufferWriteThruEnable,
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*
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* "This bit must NOT be set for >1x MSAA modes, since sampler
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* doesn't support sampling from >1x MSAA depth buffer."
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*
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* Again, this is all focused around what the sampler can do and not
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* what the depth hardware can do.
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*
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* Reading even more internal docs which can't be quoted here makes it
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* pretty clear that, even if it's not currently called out in the
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* BSpec, HiZ+CCS write-through isn't intended to work with MSAA and we
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* shouldn't try to use it. Treat it as if it's disallowed even if the
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* BSpec doesn't explicitly document that.
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*/
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if (hiz.HierarchicalDepthBufferWriteThruEnable)
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assert(info->depth_surf->samples == 1);
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#endif
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#if GFX_VER >= 8
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/* From the SKL PRM Vol2a:
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*
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* The interpretation of this field is dependent on Surface Type
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* as follows:
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* - SURFTYPE_1D: distance in pixels between array slices
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* - SURFTYPE_2D/CUBE: distance in rows between array slices
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* - SURFTYPE_3D: distance in rows between R - slices
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*
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* Unfortunately, the docs aren't 100% accurate here. They fail to
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* mention that the 1-D rule only applies to linear 1-D images.
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* Since depth and HiZ buffers are always tiled, they are treated as
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* 2-D images. Prior to Sky Lake, this field is always in rows.
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*/
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hiz.SurfaceQPitch =
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isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
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#endif
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clear.DepthClearValueValid = true;
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#if GFX_VER >= 8
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clear.DepthClearValue = info->depth_clear_value;
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#else
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switch (info->depth_surf->format) {
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case ISL_FORMAT_R32_FLOAT: {
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union { float f; uint32_t u; } fu;
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fu.f = info->depth_clear_value;
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clear.DepthClearValue = fu.u;
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break;
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}
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case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
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clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
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break;
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case ISL_FORMAT_R16_UNORM:
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clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
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break;
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default:
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unreachable("Invalid depth type");
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}
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#endif
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}
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#endif /* GFX_VER >= 6 */
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/* Pack everything into the batch */
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uint32_t *dw = batch;
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GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
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dw += GENX(3DSTATE_DEPTH_BUFFER_length);
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#if GFX_VER >= 6
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GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
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dw += GENX(3DSTATE_STENCIL_BUFFER_length);
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GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
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dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
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GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
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dw += GENX(3DSTATE_CLEAR_PARAMS_length);
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#endif
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}
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