265 lines
9.9 KiB
C
265 lines
9.9 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "genX_state_util.h"
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VkResult
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genX(init_device_state)(struct anv_device *device)
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{
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struct anv_batch batch;
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uint32_t cmds[64];
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batch.start = batch.next = cmds;
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batch.end = (void *) cmds + sizeof(cmds);
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anv_batch_emit(&batch, GENX(PIPELINE_SELECT),
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.PipelineSelection = _3D);
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anv_batch_emit(&batch, GENX(3DSTATE_VF_STATISTICS),
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.StatisticsEnable = true);
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anv_batch_emit(&batch, GENX(3DSTATE_HS), .Enable = false);
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anv_batch_emit(&batch, GENX(3DSTATE_TE), .TEEnable = false);
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anv_batch_emit(&batch, GENX(3DSTATE_DS), .DSFunctionEnable = false);
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anv_batch_emit(&batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
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anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
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anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END));
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assert(batch.next <= batch.end);
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return anv_device_submit_simple_batch(device, &batch);
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}
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void
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genX(fill_buffer_surface_state)(void *state, enum isl_format format,
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uint32_t offset, uint32_t range,
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uint32_t stride)
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{
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uint32_t num_elements = range / stride;
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struct GENX(RENDER_SURFACE_STATE) surface_state = {
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.SurfaceType = SURFTYPE_BUFFER,
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.SurfaceFormat = format,
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.SurfaceVerticalAlignment = VALIGN_4,
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.SurfaceHorizontalAlignment = HALIGN_4,
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.TiledSurface = false,
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.RenderCacheReadWriteMode = false,
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.SurfaceObjectControlState = GENX(MOCS),
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.Height = ((num_elements - 1) >> 7) & 0x3fff,
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.Width = (num_elements - 1) & 0x7f,
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.Depth = ((num_elements - 1) >> 21) & 0x3f,
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.SurfacePitch = stride - 1,
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# if (GEN_IS_HASWELL)
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.ShaderChannelSelectRed = SCS_RED,
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.ShaderChannelSelectGreen = SCS_GREEN,
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.ShaderChannelSelectBlue = SCS_BLUE,
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.ShaderChannelSelectAlpha = SCS_ALPHA,
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# endif
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.SurfaceBaseAddress = { NULL, offset },
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};
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GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
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}
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VkResult genX(CreateSampler)(
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VkDevice _device,
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const VkSamplerCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkSampler* pSampler)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_sampler *sampler;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
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sampler = anv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (!sampler)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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struct GENX(SAMPLER_STATE) sampler_state = {
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.SamplerDisable = false,
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.TextureBorderColorMode = DX10OGL,
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.LODPreClampEnable = CLAMP_ENABLE_OGL,
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.BaseMipLevel = 0.0,
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.MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
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.MagModeFilter = vk_to_gen_tex_filter(pCreateInfo->magFilter,
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pCreateInfo->anisotropyEnable),
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.MinModeFilter = vk_to_gen_tex_filter(pCreateInfo->minFilter,
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pCreateInfo->anisotropyEnable),
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.TextureLODBias = pCreateInfo->mipLodBias * 256,
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.AnisotropicAlgorithm = EWAApproximation,
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.MinLOD = pCreateInfo->minLod,
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.MaxLOD = pCreateInfo->maxLod,
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.ChromaKeyEnable = 0,
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.ChromaKeyIndex = 0,
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.ChromaKeyMode = 0,
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.ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
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.CubeSurfaceControlMode = OVERRIDE,
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.BorderColorPointer =
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device->border_colors.offset +
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pCreateInfo->borderColor * sizeof(float) * 4,
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.MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
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.RAddressMinFilterRoundingEnable = 0,
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.RAddressMagFilterRoundingEnable = 0,
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.VAddressMinFilterRoundingEnable = 0,
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.VAddressMagFilterRoundingEnable = 0,
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.UAddressMinFilterRoundingEnable = 0,
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.UAddressMagFilterRoundingEnable = 0,
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.TrilinearFilterQuality = 0,
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.NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
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.TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
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.TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
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.TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
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};
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GENX(SAMPLER_STATE_pack)(NULL, sampler->state, &sampler_state);
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*pSampler = anv_sampler_to_handle(sampler);
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return VK_SUCCESS;
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}
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static const uint8_t anv_halign[] = {
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[4] = HALIGN_4,
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[8] = HALIGN_8,
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};
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static const uint8_t anv_valign[] = {
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[2] = VALIGN_2,
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[4] = VALIGN_4,
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};
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void
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genX(fill_image_surface_state)(struct anv_device *device, void *state_map,
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struct anv_image_view *iview,
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const VkImageViewCreateInfo *pCreateInfo,
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VkImageUsageFlagBits usage)
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{
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if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
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anv_finishme("non-2D image views");
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assert(usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
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VK_IMAGE_USAGE_STORAGE_BIT |
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VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT));
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assert(util_is_power_of_two(usage));
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ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
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const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
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bool is_storage = (usage == VK_IMAGE_USAGE_STORAGE_BIT);
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struct anv_surface *surface =
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anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
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uint32_t depth = 1;
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if (range->layerCount > 1) {
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depth = range->layerCount;
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} else if (image->extent.depth > 1) {
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depth = image->extent.depth;
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}
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const struct isl_extent3d image_align_sa =
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isl_surf_get_image_alignment_sa(&surface->isl);
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struct GENX(RENDER_SURFACE_STATE) template = {
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.SurfaceType = anv_surftype(image, pCreateInfo->viewType,
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usage == VK_IMAGE_USAGE_STORAGE_BIT),
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.SurfaceArray = image->array_size > 1,
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.SurfaceFormat = anv_surface_format(device, iview->format, is_storage),
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.SurfaceVerticalAlignment = anv_valign[image_align_sa.height],
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.SurfaceHorizontalAlignment = anv_halign[image_align_sa.width],
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/* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
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* Tiled Surface is False."
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*/
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.TiledSurface = surface->isl.tiling != ISL_TILING_LINEAR,
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.TileWalk = surface->isl.tiling == ISL_TILING_Y0 ?
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TILEWALK_YMAJOR : TILEWALK_XMAJOR,
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.VerticalLineStride = 0,
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.VerticalLineStrideOffset = 0,
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.RenderCacheReadWriteMode = 0, /* TEMPLATE */
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.Height = image->extent.height - 1,
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.Width = image->extent.width - 1,
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.Depth = depth - 1,
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.SurfacePitch = surface->isl.row_pitch - 1,
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.MinimumArrayElement = range->baseArrayLayer,
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.NumberofMultisamples = MULTISAMPLECOUNT_1,
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.XOffset = 0,
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.YOffset = 0,
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.SurfaceObjectControlState = GENX(MOCS),
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.MIPCountLOD = 0, /* TEMPLATE */
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.SurfaceMinLOD = 0, /* TEMPLATE */
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.MCSEnable = false,
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# if (GEN_IS_HASWELL)
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.ShaderChannelSelectRed = vk_to_gen_swizzle[iview->swizzle.r],
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.ShaderChannelSelectGreen = vk_to_gen_swizzle[iview->swizzle.g],
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.ShaderChannelSelectBlue = vk_to_gen_swizzle[iview->swizzle.b],
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.ShaderChannelSelectAlpha = vk_to_gen_swizzle[iview->swizzle.a],
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# else /* XXX: Seriously? */
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.RedClearColor = 0,
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.GreenClearColor = 0,
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.BlueClearColor = 0,
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.AlphaClearColor = 0,
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# endif
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.ResourceMinLOD = 0.0,
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.SurfaceBaseAddress = { NULL, iview->offset },
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};
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if (usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
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/* For render target surfaces, the hardware interprets field
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* MIPCount/LOD as LOD. The Broadwell PRM says:
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*
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* MIPCountLOD defines the LOD that will be rendered into.
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* SurfaceMinLOD is ignored.
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*/
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template.MIPCountLOD = range->baseMipLevel;
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template.SurfaceMinLOD = 0;
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} else {
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/* For non render target surfaces, the hardware interprets field
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* MIPCount/LOD as MIPCount. The range of levels accessible by the
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* sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
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*/
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template.SurfaceMinLOD = range->baseMipLevel;
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template.MIPCountLOD = MAX2(range->levelCount, 1) - 1;
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}
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GENX(RENDER_SURFACE_STATE_pack)(NULL, state_map, &template);
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}
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