8278a46b26
Kernel support for DG1 has not yet been merged upstream; per our long-standing DRM subsystem policy, we should not enable the platform in userspace until the kernel patches are merged and functional. We will re-enable this in the future. In the meantime, we retain all of the infrastructure and code for the platform so that we can continue developing DG1 support in upstream. See a discussion here: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956#note_547775 Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5617>
21 lines
1.0 KiB
C
21 lines
1.0 KiB
C
CHIPSET(0x4c8a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
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CHIPSET(0x4c8b, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
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CHIPSET(0x4c8c, rkl_gt05, "RKL GT0.5", "Intel(R) Graphics")
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CHIPSET(0x4c90, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
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CHIPSET(0x4c9a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
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CHIPSET(0x9A40, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
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CHIPSET(0x9A49, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
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CHIPSET(0x9A59, tgl_gt2, "TGL GT2", "Intel(R) Graphics")
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CHIPSET(0x9A60, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
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CHIPSET(0x9A68, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
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CHIPSET(0x9A70, tgl_gt1, "TGL GT1", "Intel(R) UHD Graphics")
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CHIPSET(0x9A78, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
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CHIPSET(0x9AC0, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
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CHIPSET(0x9AC9, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
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CHIPSET(0x9AD9, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
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CHIPSET(0x9AF8, tgl_gt2, "TGL GT2", "Intel(R) UHD Graphics")
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/* Disabled for now until kernel support is ready */
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/* CHIPSET(0x4905, dg1, "DG1 GT2", "Intel(R) Graphics") */
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