aa494cbacf
In commitfe3d90aedf("intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.") we aligned the width of scratch messages to physical register sizes (32B prior to Xe2, 64B for Xe2+). But our spilling offsets are computed using the register allocations sizes which are in units of 32B. That means on Xe2, you can end up spilling a virtual register allocated at 32B (which we use for surface state computations with exec_all) and then the spilling of that register will be emitted in SIMD16, having the upper 8 lanes overwriting the next spilled register. We could potentially limit spills to SIMD8 messages on Xe2 (only writing 32B of data), but we're also unlikely to have all 32B virtual register spilled next to one another. And if not tightly packed, we would have 64B registers stored on 2 different cachelines which sounds inefficient. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes:fe3d90aedf("intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.") Backport-to: 24.2 Reviewed-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30983>
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