a96d92a689
By using the same mi_builder throughout the draw call, we can just allocate a register from the mi_builder and unref it when we're done. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
1074 lines
38 KiB
C
1074 lines
38 KiB
C
/*
|
||
* Copyright © 2015 Intel Corporation
|
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*
|
||
* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||
* and/or sell copies of the Software, and to permit persons to whom the
|
||
* Software is furnished to do so, subject to the following conditions:
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||
*
|
||
* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
|
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* Software.
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*
|
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
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* IN THE SOFTWARE.
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*/
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|
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#include <assert.h>
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#include <stdbool.h>
|
||
#include <string.h>
|
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#include <unistd.h>
|
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#include <fcntl.h>
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|
||
#include "anv_private.h"
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||
|
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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|
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/* We reserve GPR 15 for conditional rendering */
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#define GEN_MI_BUILDER_NUM_ALLOC_GPRS 15
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#define __gen_get_batch_dwords anv_batch_emit_dwords
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#define __gen_address_offset anv_address_add
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#include "common/gen_mi_builder.h"
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#include "perf/gen_perf.h"
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#include "perf/gen_perf_mdapi.h"
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||
#define OA_REPORT_N_UINT64 (256 / sizeof(uint64_t))
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VkResult genX(CreateQueryPool)(
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VkDevice _device,
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const VkQueryPoolCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkQueryPool* pQueryPool)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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const struct anv_physical_device *pdevice = device->physical;
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struct anv_query_pool *pool;
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VkResult result;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
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/* Query pool slots are made up of some number of 64-bit values packed
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* tightly together. For most query types have the first 64-bit value is
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* the "available" bit which is 0 when the query is unavailable and 1 when
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* it is available. The 64-bit values that follow are determined by the
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* type of query.
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*
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* For performance queries, we have a requirement to align OA reports at
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* 64bytes so we put those first and have the "available" bit behind
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* together with some other counters.
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*/
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uint32_t uint64s_per_slot = 1;
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|
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VkQueryPipelineStatisticFlags pipeline_statistics = 0;
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switch (pCreateInfo->queryType) {
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case VK_QUERY_TYPE_OCCLUSION:
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/* Occlusion queries have two values: begin and end. */
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uint64s_per_slot += 2;
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break;
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case VK_QUERY_TYPE_TIMESTAMP:
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/* Timestamps just have the one timestamp value */
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uint64s_per_slot += 1;
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break;
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case VK_QUERY_TYPE_PIPELINE_STATISTICS:
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pipeline_statistics = pCreateInfo->pipelineStatistics;
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/* We're going to trust this field implicitly so we need to ensure that
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* no unhandled extension bits leak in.
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*/
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pipeline_statistics &= ANV_PIPELINE_STATISTICS_MASK;
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/* Statistics queries have a min and max for every statistic */
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uint64s_per_slot += 2 * util_bitcount(pipeline_statistics);
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break;
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case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
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/* Transform feedback queries are 4 values, begin/end for
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* written/available.
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*/
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uint64s_per_slot += 4;
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break;
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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uint64s_per_slot = 72; /* 576 bytes, see layout below */
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break;
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}
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default:
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assert(!"Invalid query type");
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}
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pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (pool == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_QUERY_POOL);
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pool->type = pCreateInfo->queryType;
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pool->pipeline_statistics = pipeline_statistics;
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pool->stride = uint64s_per_slot * sizeof(uint64_t);
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pool->slots = pCreateInfo->queryCount;
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uint32_t bo_flags = 0;
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if (pdevice->supports_48bit_addresses)
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bo_flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
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if (pdevice->use_softpin)
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bo_flags |= EXEC_OBJECT_PINNED;
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if (pdevice->has_exec_async)
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bo_flags |= EXEC_OBJECT_ASYNC;
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uint64_t size = pool->slots * pool->stride;
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result = anv_device_alloc_bo(device, size,
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ANV_BO_ALLOC_MAPPED |
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ANV_BO_ALLOC_SNOOPED,
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0 /* explicit_address */,
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&pool->bo);
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if (result != VK_SUCCESS)
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goto fail;
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*pQueryPool = anv_query_pool_to_handle(pool);
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return VK_SUCCESS;
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fail:
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vk_free2(&device->vk.alloc, pAllocator, pool);
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return result;
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}
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void genX(DestroyQueryPool)(
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VkDevice _device,
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VkQueryPool _pool,
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const VkAllocationCallbacks* pAllocator)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_query_pool, pool, _pool);
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if (!pool)
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return;
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anv_device_release_bo(device, pool->bo);
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vk_object_base_finish(&pool->base);
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vk_free2(&device->vk.alloc, pAllocator, pool);
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}
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static struct anv_address
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anv_query_address(struct anv_query_pool *pool, uint32_t query)
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{
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return (struct anv_address) {
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.bo = pool->bo,
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.offset = query * pool->stride,
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};
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}
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/**
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* VK_INTEL_performance_query layout (576 bytes) :
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*
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* ------------------------------
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* | availability (8b) |
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* |----------------------------|
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* | marker (8b) |
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* |----------------------------|
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* | begin RPSTAT register (4b) |
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* |----------------------------|
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* | end RPSTAT register (4b) |
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* |----------------------------|
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* | begin perfcntr 1 & 2 (16b) |
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* |----------------------------|
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* | end perfcntr 1 & 2 (16b) |
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* |----------------------------|
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* | Unused (8b) |
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* |----------------------------|
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* | begin MI_RPC (256b) |
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* |----------------------------|
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* | end MI_RPC (256b) |
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* ------------------------------
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*/
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static uint32_t
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intel_perf_marker_offset(void)
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{
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return 8;
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}
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static uint32_t
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intel_perf_rpstart_offset(bool end)
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{
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return 16 + (end ? sizeof(uint32_t) : 0);
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}
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#if GEN_GEN >= 8 && GEN_GEN <= 11
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static uint32_t
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intel_perf_counter(bool end)
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{
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return 24 + (end ? (2 * sizeof(uint64_t)) : 0);
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}
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#endif
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static uint32_t
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intel_perf_mi_rpc_offset(bool end)
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{
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return 64 + (end ? 256 : 0);
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}
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static void
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cpu_write_query_result(void *dst_slot, VkQueryResultFlags flags,
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uint32_t value_index, uint64_t result)
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{
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if (flags & VK_QUERY_RESULT_64_BIT) {
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uint64_t *dst64 = dst_slot;
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dst64[value_index] = result;
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} else {
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uint32_t *dst32 = dst_slot;
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dst32[value_index] = result;
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}
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}
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static void *
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query_slot(struct anv_query_pool *pool, uint32_t query)
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{
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return pool->bo->map + query * pool->stride;
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}
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static bool
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query_is_available(struct anv_query_pool *pool, uint32_t query)
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{
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return *(volatile uint64_t *)query_slot(pool, query);
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}
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static VkResult
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wait_for_available(struct anv_device *device,
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struct anv_query_pool *pool, uint32_t query)
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{
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uint64_t abs_timeout = anv_get_absolute_timeout(5 * NSEC_PER_SEC);
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|
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while (anv_gettime_ns() < abs_timeout) {
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if (query_is_available(pool, query))
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return VK_SUCCESS;
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VkResult status = anv_device_query_status(device);
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if (status != VK_SUCCESS)
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return status;
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}
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return anv_device_set_lost(device, "query timeout");
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}
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VkResult genX(GetQueryPoolResults)(
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VkDevice _device,
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VkQueryPool queryPool,
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uint32_t firstQuery,
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uint32_t queryCount,
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size_t dataSize,
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void* pData,
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VkDeviceSize stride,
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VkQueryResultFlags flags)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
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assert(pool->type == VK_QUERY_TYPE_OCCLUSION ||
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pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS ||
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pool->type == VK_QUERY_TYPE_TIMESTAMP ||
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pool->type == VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT ||
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pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL);
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if (anv_device_is_lost(device))
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return VK_ERROR_DEVICE_LOST;
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||
|
||
if (pData == NULL)
|
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return VK_SUCCESS;
|
||
|
||
void *data_end = pData + dataSize;
|
||
|
||
VkResult status = VK_SUCCESS;
|
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for (uint32_t i = 0; i < queryCount; i++) {
|
||
bool available = query_is_available(pool, firstQuery + i);
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||
|
||
if (!available && (flags & VK_QUERY_RESULT_WAIT_BIT)) {
|
||
status = wait_for_available(device, pool, firstQuery + i);
|
||
if (status != VK_SUCCESS)
|
||
return status;
|
||
|
||
available = true;
|
||
}
|
||
|
||
/* From the Vulkan 1.0.42 spec:
|
||
*
|
||
* "If VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are
|
||
* both not set then no result values are written to pData for
|
||
* queries that are in the unavailable state at the time of the call,
|
||
* and vkGetQueryPoolResults returns VK_NOT_READY. However,
|
||
* availability state is still written to pData for those queries if
|
||
* VK_QUERY_RESULT_WITH_AVAILABILITY_BIT is set."
|
||
*/
|
||
bool write_results = available || (flags & VK_QUERY_RESULT_PARTIAL_BIT);
|
||
|
||
uint32_t idx = 0;
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION: {
|
||
uint64_t *slot = query_slot(pool, firstQuery + i);
|
||
if (write_results) {
|
||
/* From the Vulkan 1.2.132 spec:
|
||
*
|
||
* "If VK_QUERY_RESULT_PARTIAL_BIT is set,
|
||
* VK_QUERY_RESULT_WAIT_BIT is not set, and the query’s status
|
||
* is unavailable, an intermediate result value between zero and
|
||
* the final result value is written to pData for that query."
|
||
*/
|
||
uint64_t result = available ? slot[2] - slot[1] : 0;
|
||
cpu_write_query_result(pData, flags, idx, result);
|
||
}
|
||
idx++;
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
|
||
uint64_t *slot = query_slot(pool, firstQuery + i);
|
||
uint32_t statistics = pool->pipeline_statistics;
|
||
while (statistics) {
|
||
uint32_t stat = u_bit_scan(&statistics);
|
||
if (write_results) {
|
||
uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1];
|
||
|
||
/* WaDividePSInvocationCountBy4:HSW,BDW */
|
||
if ((device->info.gen == 8 || device->info.is_haswell) &&
|
||
(1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT)
|
||
result >>= 2;
|
||
|
||
cpu_write_query_result(pData, flags, idx, result);
|
||
}
|
||
idx++;
|
||
}
|
||
assert(idx == util_bitcount(pool->pipeline_statistics));
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: {
|
||
uint64_t *slot = query_slot(pool, firstQuery + i);
|
||
if (write_results)
|
||
cpu_write_query_result(pData, flags, idx, slot[2] - slot[1]);
|
||
idx++;
|
||
if (write_results)
|
||
cpu_write_query_result(pData, flags, idx, slot[4] - slot[3]);
|
||
idx++;
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_TIMESTAMP: {
|
||
uint64_t *slot = query_slot(pool, firstQuery + i);
|
||
if (write_results)
|
||
cpu_write_query_result(pData, flags, idx, slot[1]);
|
||
idx++;
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||
if (!write_results)
|
||
break;
|
||
const void *query_data = query_slot(pool, firstQuery + i);
|
||
const uint32_t *oa_begin = query_data + intel_perf_mi_rpc_offset(false);
|
||
const uint32_t *oa_end = query_data + intel_perf_mi_rpc_offset(true);
|
||
const uint32_t *rpstat_begin = query_data + intel_perf_rpstart_offset(false);
|
||
const uint32_t *rpstat_end = query_data + intel_perf_mi_rpc_offset(true);
|
||
struct gen_perf_query_result result;
|
||
struct gen_perf_query_info metric = {
|
||
.oa_format = (GEN_GEN >= 8 ?
|
||
I915_OA_FORMAT_A32u40_A4u32_B8_C8 :
|
||
I915_OA_FORMAT_A45_B8_C8),
|
||
};
|
||
uint32_t core_freq[2];
|
||
#if GEN_GEN < 9
|
||
core_freq[0] = ((*rpstat_begin >> 7) & 0x7f) * 1000000ULL;
|
||
core_freq[1] = ((*rpstat_end >> 7) & 0x7f) * 1000000ULL;
|
||
#else
|
||
core_freq[0] = ((*rpstat_begin >> 23) & 0x1ff) * 1000000ULL;
|
||
core_freq[1] = ((*rpstat_end >> 23) & 0x1ff) * 1000000ULL;
|
||
#endif
|
||
gen_perf_query_result_clear(&result);
|
||
gen_perf_query_result_accumulate(&result, &metric,
|
||
oa_begin, oa_end);
|
||
gen_perf_query_result_read_frequencies(&result, &device->info,
|
||
oa_begin, oa_end);
|
||
gen_perf_query_result_write_mdapi(pData, stride,
|
||
&device->info,
|
||
&result,
|
||
core_freq[0], core_freq[1]);
|
||
#if GEN_GEN >= 8 && GEN_GEN <= 11
|
||
gen_perf_query_mdapi_write_perfcntr(pData, stride, &device->info,
|
||
query_data + intel_perf_counter(false),
|
||
query_data + intel_perf_counter(true));
|
||
#endif
|
||
const uint64_t *marker = query_data + intel_perf_marker_offset();
|
||
gen_perf_query_mdapi_write_marker(pData, stride, &device->info, *marker);
|
||
break;
|
||
}
|
||
|
||
default:
|
||
unreachable("invalid pool type");
|
||
}
|
||
|
||
if (!write_results)
|
||
status = VK_NOT_READY;
|
||
|
||
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
|
||
cpu_write_query_result(pData, flags, idx, available);
|
||
|
||
pData += stride;
|
||
if (pData >= data_end)
|
||
break;
|
||
}
|
||
|
||
return status;
|
||
}
|
||
|
||
static void
|
||
emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
|
||
struct anv_address addr)
|
||
{
|
||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
|
||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.DestinationAddressType = DAT_PPGTT;
|
||
pc.PostSyncOperation = WritePSDepthCount;
|
||
pc.DepthStallEnable = true;
|
||
pc.Address = addr;
|
||
|
||
if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
|
||
pc.CommandStreamerStallEnable = true;
|
||
}
|
||
}
|
||
|
||
static void
|
||
emit_query_mi_availability(struct gen_mi_builder *b,
|
||
struct anv_address addr,
|
||
bool available)
|
||
{
|
||
gen_mi_store(b, gen_mi_mem64(addr), gen_mi_imm(available));
|
||
}
|
||
|
||
static void
|
||
emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,
|
||
struct anv_address addr,
|
||
bool available)
|
||
{
|
||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
|
||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.DestinationAddressType = DAT_PPGTT;
|
||
pc.PostSyncOperation = WriteImmediateData;
|
||
pc.Address = addr;
|
||
pc.ImmediateData = available;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* Goes through a series of consecutive query indices in the given pool
|
||
* setting all element values to 0 and emitting them as available.
|
||
*/
|
||
static void
|
||
emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
|
||
struct gen_mi_builder *b, struct anv_query_pool *pool,
|
||
uint32_t first_index, uint32_t num_queries)
|
||
{
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION:
|
||
case VK_QUERY_TYPE_TIMESTAMP:
|
||
/* These queries are written with a PIPE_CONTROL so clear them using the
|
||
* PIPE_CONTROL as well so we don't have to synchronize between 2 types
|
||
* of operations.
|
||
*/
|
||
assert((pool->stride % 8) == 0);
|
||
for (uint32_t i = 0; i < num_queries; i++) {
|
||
struct anv_address slot_addr =
|
||
anv_query_address(pool, first_index + i);
|
||
|
||
for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) {
|
||
emit_query_pc_availability(cmd_buffer,
|
||
anv_address_add(slot_addr, qword * 8),
|
||
false);
|
||
}
|
||
emit_query_pc_availability(cmd_buffer, slot_addr, true);
|
||
}
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
|
||
for (uint32_t i = 0; i < num_queries; i++) {
|
||
struct anv_address slot_addr =
|
||
anv_query_address(pool, first_index + i);
|
||
gen_mi_memset(b, anv_address_add(slot_addr, 8), 0, pool->stride - 8);
|
||
emit_query_mi_availability(b, slot_addr, true);
|
||
}
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL:
|
||
for (uint32_t i = 0; i < num_queries; i++) {
|
||
struct anv_address slot_addr =
|
||
anv_query_address(pool, first_index + i);
|
||
gen_mi_memset(b, anv_address_add(slot_addr, 8), 0, pool->stride - 8);
|
||
emit_query_mi_availability(b, slot_addr, true);
|
||
}
|
||
break;
|
||
|
||
default:
|
||
unreachable("Unsupported query type");
|
||
}
|
||
}
|
||
|
||
void genX(CmdResetQueryPool)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t firstQuery,
|
||
uint32_t queryCount)
|
||
{
|
||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION:
|
||
case VK_QUERY_TYPE_TIMESTAMP:
|
||
for (uint32_t i = 0; i < queryCount; i++) {
|
||
emit_query_pc_availability(cmd_buffer,
|
||
anv_query_address(pool, firstQuery + i),
|
||
false);
|
||
}
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: {
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
|
||
for (uint32_t i = 0; i < queryCount; i++)
|
||
emit_query_mi_availability(&b, anv_query_address(pool, firstQuery + i), false);
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
|
||
for (uint32_t i = 0; i < queryCount; i++)
|
||
emit_query_mi_availability(&b, anv_query_address(pool, firstQuery + i), false);
|
||
break;
|
||
}
|
||
|
||
default:
|
||
unreachable("Unsupported query type");
|
||
}
|
||
}
|
||
|
||
void genX(ResetQueryPool)(
|
||
VkDevice _device,
|
||
VkQueryPool queryPool,
|
||
uint32_t firstQuery,
|
||
uint32_t queryCount)
|
||
{
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
|
||
for (uint32_t i = 0; i < queryCount; i++) {
|
||
uint64_t *slot = query_slot(pool, firstQuery + i);
|
||
*slot = 0;
|
||
}
|
||
}
|
||
|
||
static const uint32_t vk_pipeline_stat_to_reg[] = {
|
||
GENX(IA_VERTICES_COUNT_num),
|
||
GENX(IA_PRIMITIVES_COUNT_num),
|
||
GENX(VS_INVOCATION_COUNT_num),
|
||
GENX(GS_INVOCATION_COUNT_num),
|
||
GENX(GS_PRIMITIVES_COUNT_num),
|
||
GENX(CL_INVOCATION_COUNT_num),
|
||
GENX(CL_PRIMITIVES_COUNT_num),
|
||
GENX(PS_INVOCATION_COUNT_num),
|
||
GENX(HS_INVOCATION_COUNT_num),
|
||
GENX(DS_INVOCATION_COUNT_num),
|
||
GENX(CS_INVOCATION_COUNT_num),
|
||
};
|
||
|
||
static void
|
||
emit_pipeline_stat(struct gen_mi_builder *b, uint32_t stat,
|
||
struct anv_address addr)
|
||
{
|
||
STATIC_ASSERT(ANV_PIPELINE_STATISTICS_MASK ==
|
||
(1 << ARRAY_SIZE(vk_pipeline_stat_to_reg)) - 1);
|
||
|
||
assert(stat < ARRAY_SIZE(vk_pipeline_stat_to_reg));
|
||
gen_mi_store(b, gen_mi_mem64(addr),
|
||
gen_mi_reg64(vk_pipeline_stat_to_reg[stat]));
|
||
}
|
||
|
||
static void
|
||
emit_xfb_query(struct gen_mi_builder *b, uint32_t stream,
|
||
struct anv_address addr)
|
||
{
|
||
assert(stream < MAX_XFB_STREAMS);
|
||
|
||
gen_mi_store(b, gen_mi_mem64(anv_address_add(addr, 0)),
|
||
gen_mi_reg64(GENX(SO_NUM_PRIMS_WRITTEN0_num) + stream * 8));
|
||
gen_mi_store(b, gen_mi_mem64(anv_address_add(addr, 16)),
|
||
gen_mi_reg64(GENX(SO_PRIM_STORAGE_NEEDED0_num) + stream * 8));
|
||
}
|
||
|
||
void genX(CmdBeginQuery)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t query,
|
||
VkQueryControlFlags flags)
|
||
{
|
||
genX(CmdBeginQueryIndexedEXT)(commandBuffer, queryPool, query, flags, 0);
|
||
}
|
||
|
||
void genX(CmdBeginQueryIndexedEXT)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t query,
|
||
VkQueryControlFlags flags,
|
||
uint32_t index)
|
||
{
|
||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
struct anv_address query_addr = anv_query_address(pool, query);
|
||
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION:
|
||
emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 8));
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
|
||
/* TODO: This might only be necessary for certain stats */
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
|
||
uint32_t statistics = pool->pipeline_statistics;
|
||
uint32_t offset = 8;
|
||
while (statistics) {
|
||
uint32_t stat = u_bit_scan(&statistics);
|
||
emit_pipeline_stat(&b, stat, anv_address_add(query_addr, offset));
|
||
offset += 16;
|
||
}
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
emit_xfb_query(&b, index, anv_address_add(query_addr, 8));
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {
|
||
rpc.MemoryAddress =
|
||
anv_address_add(query_addr, intel_perf_mi_rpc_offset(false));
|
||
}
|
||
#if GEN_GEN < 9
|
||
gen_mi_store(&b,
|
||
gen_mi_mem32(anv_address_add(query_addr,
|
||
intel_perf_rpstart_offset(false))),
|
||
gen_mi_reg32(GENX(RPSTAT1_num)));
|
||
#else
|
||
gen_mi_store(&b,
|
||
gen_mi_mem32(anv_address_add(query_addr,
|
||
intel_perf_rpstart_offset(false))),
|
||
gen_mi_reg32(GENX(RPSTAT0_num)));
|
||
#endif
|
||
#if GEN_GEN >= 8 && GEN_GEN <= 11
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr,
|
||
intel_perf_counter(false))),
|
||
gen_mi_reg64(GENX(PERFCNT1_num)));
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr,
|
||
intel_perf_counter(false) + 8)),
|
||
gen_mi_reg64(GENX(PERFCNT2_num)));
|
||
#endif
|
||
break;
|
||
}
|
||
|
||
default:
|
||
unreachable("");
|
||
}
|
||
}
|
||
|
||
void genX(CmdEndQuery)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t query)
|
||
{
|
||
genX(CmdEndQueryIndexedEXT)(commandBuffer, queryPool, query, 0);
|
||
}
|
||
|
||
void genX(CmdEndQueryIndexedEXT)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t query,
|
||
uint32_t index)
|
||
{
|
||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
struct anv_address query_addr = anv_query_address(pool, query);
|
||
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION:
|
||
emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 16));
|
||
emit_query_pc_availability(cmd_buffer, query_addr, true);
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
|
||
/* TODO: This might only be necessary for certain stats */
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
|
||
uint32_t statistics = pool->pipeline_statistics;
|
||
uint32_t offset = 16;
|
||
while (statistics) {
|
||
uint32_t stat = u_bit_scan(&statistics);
|
||
emit_pipeline_stat(&b, stat, anv_address_add(query_addr, offset));
|
||
offset += 16;
|
||
}
|
||
|
||
emit_query_mi_availability(&b, query_addr, true);
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
|
||
emit_xfb_query(&b, index, anv_address_add(query_addr, 16));
|
||
emit_query_mi_availability(&b, query_addr, true);
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.CommandStreamerStallEnable = true;
|
||
pc.StallAtPixelScoreboard = true;
|
||
}
|
||
uint32_t marker_offset = intel_perf_marker_offset();
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, marker_offset)),
|
||
gen_mi_imm(cmd_buffer->intel_perf_marker));
|
||
#if GEN_GEN >= 8 && GEN_GEN <= 11
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, intel_perf_counter(true))),
|
||
gen_mi_reg64(GENX(PERFCNT1_num)));
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, intel_perf_counter(true) + 8)),
|
||
gen_mi_reg64(GENX(PERFCNT2_num)));
|
||
#endif
|
||
#if GEN_GEN < 9
|
||
gen_mi_store(&b,
|
||
gen_mi_mem32(anv_address_add(query_addr,
|
||
intel_perf_rpstart_offset(true))),
|
||
gen_mi_reg32(GENX(RPSTAT1_num)));
|
||
#else
|
||
gen_mi_store(&b,
|
||
gen_mi_mem32(anv_address_add(query_addr,
|
||
intel_perf_rpstart_offset(true))),
|
||
gen_mi_reg32(GENX(RPSTAT0_num)));
|
||
#endif
|
||
/* Position the last OA snapshot at the beginning of the query so that
|
||
* we can tell whether it's ready.
|
||
*/
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {
|
||
rpc.MemoryAddress = anv_address_add(query_addr,
|
||
intel_perf_mi_rpc_offset(true));
|
||
rpc.ReportID = 0xdeadbeef; /* This goes in the first dword */
|
||
}
|
||
emit_query_mi_availability(&b, query_addr, true);
|
||
break;
|
||
}
|
||
|
||
default:
|
||
unreachable("");
|
||
}
|
||
|
||
/* When multiview is active the spec requires that N consecutive query
|
||
* indices are used, where N is the number of active views in the subpass.
|
||
* The spec allows that we only write the results to one of the queries
|
||
* but we still need to manage result availability for all the query indices.
|
||
* Since we only emit a single query for all active views in the
|
||
* first index, mark the other query indices as being already available
|
||
* with result 0.
|
||
*/
|
||
if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
|
||
const uint32_t num_queries =
|
||
util_bitcount(cmd_buffer->state.subpass->view_mask);
|
||
if (num_queries > 1)
|
||
emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);
|
||
}
|
||
}
|
||
|
||
#define TIMESTAMP 0x2358
|
||
|
||
void genX(CmdWriteTimestamp)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkPipelineStageFlagBits pipelineStage,
|
||
VkQueryPool queryPool,
|
||
uint32_t query)
|
||
{
|
||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
struct anv_address query_addr = anv_query_address(pool, query);
|
||
|
||
assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
|
||
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
|
||
switch (pipelineStage) {
|
||
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
|
||
gen_mi_store(&b, gen_mi_mem64(anv_address_add(query_addr, 8)),
|
||
gen_mi_reg64(TIMESTAMP));
|
||
break;
|
||
|
||
default:
|
||
/* Everything else is bottom-of-pipe */
|
||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
|
||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
|
||
pc.DestinationAddressType = DAT_PPGTT;
|
||
pc.PostSyncOperation = WriteTimestamp;
|
||
pc.Address = anv_address_add(query_addr, 8);
|
||
|
||
if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
|
||
pc.CommandStreamerStallEnable = true;
|
||
}
|
||
break;
|
||
}
|
||
|
||
emit_query_pc_availability(cmd_buffer, query_addr, true);
|
||
|
||
/* When multiview is active the spec requires that N consecutive query
|
||
* indices are used, where N is the number of active views in the subpass.
|
||
* The spec allows that we only write the results to one of the queries
|
||
* but we still need to manage result availability for all the query indices.
|
||
* Since we only emit a single query for all active views in the
|
||
* first index, mark the other query indices as being already available
|
||
* with result 0.
|
||
*/
|
||
if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
|
||
const uint32_t num_queries =
|
||
util_bitcount(cmd_buffer->state.subpass->view_mask);
|
||
if (num_queries > 1)
|
||
emit_zero_queries(cmd_buffer, &b, pool, query + 1, num_queries - 1);
|
||
}
|
||
}
|
||
|
||
#if GEN_GEN > 7 || GEN_IS_HASWELL
|
||
|
||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||
|
||
#define MI_PREDICATE_SRC0 0x2400
|
||
#define MI_PREDICATE_SRC1 0x2408
|
||
#define MI_PREDICATE_RESULT 0x2418
|
||
|
||
/**
|
||
* Writes the results of a query to dst_addr is the value at poll_addr is equal
|
||
* to the reference value.
|
||
*/
|
||
static void
|
||
gpu_write_query_result_cond(struct anv_cmd_buffer *cmd_buffer,
|
||
struct gen_mi_builder *b,
|
||
struct anv_address poll_addr,
|
||
struct anv_address dst_addr,
|
||
uint64_t ref_value,
|
||
VkQueryResultFlags flags,
|
||
uint32_t value_index,
|
||
struct gen_mi_value query_result)
|
||
{
|
||
gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0), gen_mi_mem64(poll_addr));
|
||
gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(ref_value));
|
||
anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
|
||
mip.LoadOperation = LOAD_LOAD;
|
||
mip.CombineOperation = COMBINE_SET;
|
||
mip.CompareOperation = COMPARE_SRCS_EQUAL;
|
||
}
|
||
|
||
if (flags & VK_QUERY_RESULT_64_BIT) {
|
||
struct anv_address res_addr = anv_address_add(dst_addr, value_index * 8);
|
||
gen_mi_store_if(b, gen_mi_mem64(res_addr), query_result);
|
||
} else {
|
||
struct anv_address res_addr = anv_address_add(dst_addr, value_index * 4);
|
||
gen_mi_store_if(b, gen_mi_mem32(res_addr), query_result);
|
||
}
|
||
}
|
||
|
||
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
|
||
|
||
static void
|
||
gpu_write_query_result(struct gen_mi_builder *b,
|
||
struct anv_address dst_addr,
|
||
VkQueryResultFlags flags,
|
||
uint32_t value_index,
|
||
struct gen_mi_value query_result)
|
||
{
|
||
if (flags & VK_QUERY_RESULT_64_BIT) {
|
||
struct anv_address res_addr = anv_address_add(dst_addr, value_index * 8);
|
||
gen_mi_store(b, gen_mi_mem64(res_addr), query_result);
|
||
} else {
|
||
struct anv_address res_addr = anv_address_add(dst_addr, value_index * 4);
|
||
gen_mi_store(b, gen_mi_mem32(res_addr), query_result);
|
||
}
|
||
}
|
||
|
||
static struct gen_mi_value
|
||
compute_query_result(struct gen_mi_builder *b, struct anv_address addr)
|
||
{
|
||
return gen_mi_isub(b, gen_mi_mem64(anv_address_add(addr, 8)),
|
||
gen_mi_mem64(anv_address_add(addr, 0)));
|
||
}
|
||
|
||
void genX(CmdCopyQueryPoolResults)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t firstQuery,
|
||
uint32_t queryCount,
|
||
VkBuffer destBuffer,
|
||
VkDeviceSize destOffset,
|
||
VkDeviceSize destStride,
|
||
VkQueryResultFlags flags)
|
||
{
|
||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
|
||
ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
|
||
|
||
struct gen_mi_builder b;
|
||
gen_mi_builder_init(&b, &cmd_buffer->batch);
|
||
struct gen_mi_value result;
|
||
|
||
/* If render target writes are ongoing, request a render target cache flush
|
||
* to ensure proper ordering of the commands from the 3d pipe and the
|
||
* command streamer.
|
||
*/
|
||
if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_BUFFER_WRITES) {
|
||
cmd_buffer->state.pending_pipe_bits |=
|
||
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
|
||
}
|
||
|
||
if ((flags & VK_QUERY_RESULT_WAIT_BIT) ||
|
||
(cmd_buffer->state.pending_pipe_bits & ANV_PIPE_FLUSH_BITS) ||
|
||
/* Occlusion & timestamp queries are written using a PIPE_CONTROL and
|
||
* because we're about to copy values from MI commands, we need to
|
||
* stall the command streamer to make sure the PIPE_CONTROL values have
|
||
* landed, otherwise we could see inconsistent values & availability.
|
||
*
|
||
* From the vulkan spec:
|
||
*
|
||
* "vkCmdCopyQueryPoolResults is guaranteed to see the effect of
|
||
* previous uses of vkCmdResetQueryPool in the same queue, without
|
||
* any additional synchronization."
|
||
*/
|
||
pool->type == VK_QUERY_TYPE_OCCLUSION ||
|
||
pool->type == VK_QUERY_TYPE_TIMESTAMP) {
|
||
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
|
||
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
|
||
}
|
||
|
||
struct anv_address dest_addr = anv_address_add(buffer->address, destOffset);
|
||
for (uint32_t i = 0; i < queryCount; i++) {
|
||
struct anv_address query_addr = anv_query_address(pool, firstQuery + i);
|
||
uint32_t idx = 0;
|
||
switch (pool->type) {
|
||
case VK_QUERY_TYPE_OCCLUSION:
|
||
result = compute_query_result(&b, anv_address_add(query_addr, 8));
|
||
#if GEN_GEN >= 8 || GEN_IS_HASWELL
|
||
/* Like in the case of vkGetQueryPoolResults, if the query is
|
||
* unavailable and the VK_QUERY_RESULT_PARTIAL_BIT flag is set,
|
||
* conservatively write 0 as the query result. If the
|
||
* VK_QUERY_RESULT_PARTIAL_BIT isn't set, don't write any value.
|
||
*/
|
||
gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,
|
||
1 /* available */, flags, idx, result);
|
||
if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
|
||
gpu_write_query_result_cond(cmd_buffer, &b, query_addr, dest_addr,
|
||
0 /* unavailable */, flags, idx, gen_mi_imm(0));
|
||
}
|
||
idx++;
|
||
#else /* GEN_GEN < 8 && !GEN_IS_HASWELL */
|
||
gpu_write_query_result(&b, dest_addr, flags, idx++, result);
|
||
#endif
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
|
||
uint32_t statistics = pool->pipeline_statistics;
|
||
while (statistics) {
|
||
uint32_t stat = u_bit_scan(&statistics);
|
||
|
||
result = compute_query_result(&b, anv_address_add(query_addr,
|
||
idx * 16 + 8));
|
||
|
||
/* WaDividePSInvocationCountBy4:HSW,BDW */
|
||
if ((cmd_buffer->device->info.gen == 8 ||
|
||
cmd_buffer->device->info.is_haswell) &&
|
||
(1 << stat) == VK_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT) {
|
||
result = gen_mi_ushr32_imm(&b, result, 2);
|
||
}
|
||
|
||
gpu_write_query_result(&b, dest_addr, flags, idx++, result);
|
||
}
|
||
assert(idx == util_bitcount(pool->pipeline_statistics));
|
||
break;
|
||
}
|
||
|
||
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
|
||
result = compute_query_result(&b, anv_address_add(query_addr, 8));
|
||
gpu_write_query_result(&b, dest_addr, flags, idx++, result);
|
||
result = compute_query_result(&b, anv_address_add(query_addr, 24));
|
||
gpu_write_query_result(&b, dest_addr, flags, idx++, result);
|
||
break;
|
||
|
||
case VK_QUERY_TYPE_TIMESTAMP:
|
||
result = gen_mi_mem64(anv_address_add(query_addr, 8));
|
||
gpu_write_query_result(&b, dest_addr, flags, 0, result);
|
||
break;
|
||
|
||
default:
|
||
unreachable("unhandled query type");
|
||
}
|
||
|
||
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
|
||
gpu_write_query_result(&b, dest_addr, flags, idx,
|
||
gen_mi_mem64(query_addr));
|
||
}
|
||
|
||
dest_addr = anv_address_add(dest_addr, destStride);
|
||
}
|
||
}
|
||
|
||
#else
|
||
void genX(CmdCopyQueryPoolResults)(
|
||
VkCommandBuffer commandBuffer,
|
||
VkQueryPool queryPool,
|
||
uint32_t firstQuery,
|
||
uint32_t queryCount,
|
||
VkBuffer destBuffer,
|
||
VkDeviceSize destOffset,
|
||
VkDeviceSize destStride,
|
||
VkQueryResultFlags flags)
|
||
{
|
||
anv_finishme("Queries not yet supported on Ivy Bridge");
|
||
}
|
||
#endif
|