147 lines
4.6 KiB
C++
147 lines
4.6 KiB
C++
//===-- R600ISelLowering.cpp - TODO: Add brief description -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TODO: Add full description
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//
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//===----------------------------------------------------------------------===//
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM),
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TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
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{
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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// setSchedulingPreference(Sched::VLIW);
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addRegisterClass(MVT::v4f32, &AMDIL::R600_Reg128RegClass);
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addRegisterClass(MVT::f32, &AMDIL::R600_Reg32RegClass);
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addRegisterClass(MVT::v4i32, &AMDIL::R600_Reg128RegClass);
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addRegisterClass(MVT::i32, &AMDIL::R600_Reg32RegClass);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
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}
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MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const
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{
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MachineFunction * MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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switch (MI->getOpcode()) {
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default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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/* XXX: Use helper function from AMDGPULowerShaderInstructions here */
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case AMDIL::TGID_X:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T1_X);
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break;
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case AMDIL::TGID_Y:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Y);
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break;
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case AMDIL::TGID_Z:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Z);
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break;
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case AMDIL::TIDIG_X:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T0_X);
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break;
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case AMDIL::TIDIG_Y:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Y);
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break;
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case AMDIL::TIDIG_Z:
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addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Z);
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break;
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case AMDIL::NGROUPS_X:
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lowerImplicitParameter(MI, *BB, MRI, 0);
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break;
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case AMDIL::NGROUPS_Y:
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lowerImplicitParameter(MI, *BB, MRI, 1);
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break;
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case AMDIL::NGROUPS_Z:
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lowerImplicitParameter(MI, *BB, MRI, 2);
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break;
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case AMDIL::GLOBAL_SIZE_X:
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lowerImplicitParameter(MI, *BB, MRI, 3);
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break;
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case AMDIL::GLOBAL_SIZE_Y:
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lowerImplicitParameter(MI, *BB, MRI, 4);
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break;
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case AMDIL::GLOBAL_SIZE_Z:
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lowerImplicitParameter(MI, *BB, MRI, 5);
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break;
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case AMDIL::LOCAL_SIZE_X:
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lowerImplicitParameter(MI, *BB, MRI, 6);
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break;
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case AMDIL::LOCAL_SIZE_Y:
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lowerImplicitParameter(MI, *BB, MRI, 7);
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break;
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case AMDIL::LOCAL_SIZE_Z:
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lowerImplicitParameter(MI, *BB, MRI, 8);
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break;
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case AMDIL::LOAD_INPUT:
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{
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int64_t RegIndex = MI->getOperand(1).getImm();
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addLiveIn(MI, MF, MRI, TII,
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AMDIL::R600_TReg32RegClass.getRegister(RegIndex));
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MI->eraseFromParent();
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break;
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}
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case AMDIL::STORE_OUTPUT:
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{
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MachineBasicBlock::iterator I = *MI;
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int64_t OutputIndex = MI->getOperand(1).getImm();
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unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY), OutputReg)
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.addOperand(MI->getOperand(0));
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if (!MRI.isLiveOut(OutputReg)) {
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MRI.addLiveOut(OutputReg);
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}
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MI->eraseFromParent();
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break;
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}
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case AMDIL::RESERVE_REG:
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{
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R600MachineFunctionInfo * MFI = MF->getInfo<R600MachineFunctionInfo>();
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int64_t ReservedIndex = MI->getOperand(0).getImm();
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unsigned ReservedReg =
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AMDIL::R600_TReg32RegClass.getRegister(ReservedIndex);
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MFI->ReservedRegs.push_back(ReservedReg);
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MI->eraseFromParent();
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break;
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}
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}
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return BB;
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}
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void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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MachineRegisterInfo & MRI, unsigned dword_offset) const
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{
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MachineBasicBlock::iterator I = *MI;
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unsigned offsetReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
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MRI.setRegClass(MI->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), offsetReg)
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.addReg(AMDIL::ALU_LITERAL_X)
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.addImm(dword_offset * 4);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_eg))
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.addOperand(MI->getOperand(0))
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.addReg(offsetReg)
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.addImm(0);
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}
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