a288708506
This is the same as the need_dest parameter to prepare_alu_destination_and_sources. This allows us to not change the register that is expected to hold an result if an instruction is re-emitted. This is particularly a problem if the re-emitted instruction is a partial write. A later patch will use this feature. No shader-db changes on any Intel platform. v2: Don't do the Boolean resolve when there is no destination. If the ALU instruction didn't write a register, there's nothing to resolve. This replaces an earlier patch "intel/fs: Allocate dummy destination register when need_dest is false". Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
592 lines
22 KiB
C++
592 lines
22 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef BRW_FS_H
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#define BRW_FS_H
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#include "brw_shader.h"
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#include "brw_ir_fs.h"
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#include "brw_fs_builder.h"
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#include "compiler/nir/nir.h"
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struct bblock_t;
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namespace {
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struct acp_entry;
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}
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namespace brw {
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class fs_live_variables;
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}
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struct brw_gs_compile;
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static inline fs_reg
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offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta)
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{
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return offset(reg, bld.dispatch_width(), delta);
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}
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#define UBO_START ((1 << 16) - 4)
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/**
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* The fragment shader front-end.
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*
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* Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
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*/
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class fs_visitor : public backend_shader
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{
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public:
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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const void *key,
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struct brw_stage_prog_data *prog_data,
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struct gl_program *prog,
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const nir_shader *shader,
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unsigned dispatch_width,
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int shader_time_index,
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const struct brw_vue_map *input_vue_map = NULL);
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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struct brw_gs_compile *gs_compile,
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struct brw_gs_prog_data *prog_data,
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const nir_shader *shader,
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int shader_time_index);
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void init();
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~fs_visitor();
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fs_reg vgrf(const glsl_type *const type);
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void import_uniforms(fs_visitor *v);
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void setup_uniform_clipplane_values();
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void compute_clip_distance();
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void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
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const fs_reg &dst,
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const fs_reg &surf_index,
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const fs_reg &varying_offset,
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uint32_t const_offset);
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void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
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bool run_fs(bool allow_spilling, bool do_rep_send);
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bool run_vs();
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bool run_tcs();
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bool run_tes();
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bool run_gs();
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bool run_cs(unsigned min_dispatch_width);
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void optimize();
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void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
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void setup_fs_payload_gen4();
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void setup_fs_payload_gen6();
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void setup_vs_payload();
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void setup_gs_payload();
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void setup_cs_payload();
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bool fixup_sends_duplicate_payload();
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void fixup_3src_null_dest();
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void assign_curb_setup();
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void calculate_urb_setup();
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void assign_urb_setup();
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void convert_attr_sources_to_hw_regs(fs_inst *inst);
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void assign_vs_urb_setup();
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void assign_tcs_urb_setup();
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void assign_tes_urb_setup();
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void assign_gs_urb_setup();
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bool assign_regs(bool allow_spilling, bool spill_all);
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void assign_regs_trivial();
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void calculate_payload_ranges(int payload_node_count,
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int *payload_last_use_ip);
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void split_virtual_grfs();
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bool compact_virtual_grfs();
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void assign_constant_locations();
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bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
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unsigned *out_pull_index);
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void lower_constant_loads();
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void invalidate_live_intervals();
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void calculate_live_intervals();
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void calculate_register_pressure();
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void validate();
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bool opt_algebraic();
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bool opt_redundant_discard_jumps();
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bool opt_cse();
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bool opt_cse_local(bblock_t *block);
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bool opt_copy_propagation();
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bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
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bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
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bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
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exec_list *acp);
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bool opt_drop_redundant_mov_to_flags();
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bool opt_register_renaming();
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bool opt_bank_conflicts();
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unsigned bank_conflict_cycles(const fs_inst *inst) const;
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bool register_coalesce();
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bool compute_to_mrf();
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bool eliminate_find_live_channel();
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bool dead_code_eliminate();
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bool remove_duplicate_mrf_writes();
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bool remove_extra_rounding_modes();
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bool opt_sampler_eot();
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bool virtual_grf_interferes(int a, int b);
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void schedule_instructions(instruction_scheduler_mode mode);
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void insert_gen4_send_dependency_workarounds();
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void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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void vfail(const char *msg, va_list args);
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void fail(const char *msg, ...);
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void limit_dispatch_width(unsigned n, const char *msg);
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void lower_uniform_pull_constant_loads();
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bool lower_load_payload();
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bool lower_pack();
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bool lower_regioning();
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bool lower_logical_sends();
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bool lower_linterp();
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bool lower_integer_multiplication();
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bool lower_minmax();
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bool lower_simd_width();
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bool opt_combine_constants();
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void emit_dummy_fs();
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void emit_repclear_shader();
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void emit_fragcoord_interpolation(fs_reg wpos);
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fs_reg *emit_frontfacing_interpolation();
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fs_reg *emit_samplepos_setup();
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fs_reg *emit_sampleid_setup();
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fs_reg *emit_samplemaskin_setup();
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void emit_interpolation_setup_gen4();
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void emit_interpolation_setup_gen6();
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void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
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fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
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const fs_reg &texture,
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const fs_reg &texture_handle);
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void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
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fs_reg resolve_source_modifiers(const fs_reg &src);
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void emit_discard_jump();
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void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
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fs_reg result, fs_reg *op, unsigned fsign_src);
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bool opt_peephole_sel();
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bool opt_peephole_csel();
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bool opt_peephole_predicated_break();
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bool opt_saturate_propagation();
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bool opt_cmod_propagation();
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bool opt_zero_samples();
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void set_tcs_invocation_id();
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void emit_nir_code();
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void nir_setup_outputs();
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void nir_setup_uniforms();
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void nir_emit_system_values();
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void nir_emit_impl(nir_function_impl *impl);
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void nir_emit_cf_list(exec_list *list);
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void nir_emit_if(nir_if *if_stmt);
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void nir_emit_loop(nir_loop *loop);
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void nir_emit_block(nir_block *block);
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void nir_emit_instr(nir_instr *instr);
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void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
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bool need_dest);
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bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
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nir_alu_instr *instr);
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void nir_emit_load_const(const brw::fs_builder &bld,
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nir_load_const_instr *instr);
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void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_shared_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_global_atomic(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_global_atomic_float(const brw::fs_builder &bld,
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int op, nir_intrinsic_instr *instr);
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void nir_emit_texture(const brw::fs_builder &bld,
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nir_tex_instr *instr);
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void nir_emit_jump(const brw::fs_builder &bld,
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nir_jump_instr *instr);
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fs_reg get_nir_src(const nir_src &src);
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fs_reg get_nir_src_imm(const nir_src &src);
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fs_reg get_nir_dest(const nir_dest &dest);
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fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
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fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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struct brw_reg get_tcs_output_urb_handle();
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void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
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unsigned wr_mask);
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bool optimize_extract_to_float(nir_alu_instr *instr,
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const fs_reg &result);
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bool optimize_frontfacing_ternary(nir_alu_instr *instr,
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const fs_reg &result);
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void emit_alpha_test();
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fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
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fs_reg color1, fs_reg color2,
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fs_reg src0_alpha, unsigned components);
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void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha);
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void emit_fb_writes();
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fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
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const fs_reg &dst, unsigned target);
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void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
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void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
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unsigned stream_id);
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void emit_gs_control_data_bits(const fs_reg &vertex_count);
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void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
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void emit_gs_vertex(const nir_src &vertex_count_nir_src,
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unsigned stream_id);
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void emit_gs_thread_end();
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void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
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unsigned base_offset, const nir_src &offset_src,
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unsigned num_components, unsigned first_component);
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void emit_cs_terminate();
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fs_reg *emit_cs_work_group_id_setup();
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void emit_barrier();
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void emit_shader_time_begin();
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void emit_shader_time_end();
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void SHADER_TIME_ADD(const brw::fs_builder &bld,
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int shader_time_subindex,
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fs_reg value);
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fs_reg get_timestamp(const brw::fs_builder &bld);
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fs_reg interp_reg(int location, int channel);
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int implied_mrf_writes(fs_inst *inst) const;
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virtual void dump_instructions();
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virtual void dump_instructions(const char *name);
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void dump_instruction(backend_instruction *inst);
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void dump_instruction(backend_instruction *inst, FILE *file);
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const void *const key;
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const struct brw_sampler_prog_key_data *key_tex;
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struct brw_gs_compile *gs_compile;
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struct brw_stage_prog_data *prog_data;
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struct gl_program *prog;
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const struct brw_vue_map *input_vue_map;
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int *virtual_grf_start;
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int *virtual_grf_end;
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brw::fs_live_variables *live_intervals;
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int *regs_live_at_ip;
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/** Number of uniform variable components visited. */
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unsigned uniforms;
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/** Byte-offset for the next available spot in the scratch space buffer. */
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unsigned last_scratch;
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/**
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* Array mapping UNIFORM register numbers to the pull parameter index,
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* or -1 if this uniform register isn't being uploaded as a pull constant.
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*/
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int *pull_constant_loc;
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/**
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* Array mapping UNIFORM register numbers to the push parameter index,
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* or -1 if this uniform register isn't being uploaded as a push constant.
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*/
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int *push_constant_loc;
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fs_reg subgroup_id;
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fs_reg frag_depth;
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fs_reg frag_stencil;
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fs_reg sample_mask;
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fs_reg outputs[VARYING_SLOT_MAX];
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fs_reg dual_src_output;
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int first_non_payload_grf;
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/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
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unsigned max_grf;
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fs_reg *nir_locals;
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fs_reg *nir_ssa_values;
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fs_reg *nir_system_values;
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bool failed;
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char *fail_msg;
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/** Register numbers for thread payload fields. */
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struct thread_payload {
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uint8_t subspan_coord_reg[2];
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uint8_t source_depth_reg[2];
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uint8_t source_w_reg[2];
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uint8_t aa_dest_stencil_reg[2];
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uint8_t dest_depth_reg[2];
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uint8_t sample_pos_reg[2];
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uint8_t sample_mask_in_reg[2];
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uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
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uint8_t local_invocation_id_reg[2];
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/** The number of thread payload registers the hardware will supply. */
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uint8_t num_regs;
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} payload;
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bool source_depth_to_render_target;
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bool runtime_check_aads_emit;
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fs_reg pixel_x;
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fs_reg pixel_y;
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fs_reg wpos_w;
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fs_reg pixel_w;
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fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
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fs_reg shader_start_time;
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fs_reg userplane[MAX_CLIP_PLANES];
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fs_reg final_gs_vertex_count;
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fs_reg control_data_bits;
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fs_reg invocation_id;
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unsigned grf_used;
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bool spilled_any_registers;
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const unsigned dispatch_width; /**< 8, 16 or 32 */
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unsigned max_dispatch_width;
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int shader_time_index;
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unsigned promoted_constants;
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brw::fs_builder bld;
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private:
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fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
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nir_alu_instr *instr,
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fs_reg *op,
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bool need_dest);
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void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
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fs_reg *op);
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};
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/**
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* The fragment shader code generator.
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*
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* Translates FS IR to actual i965 assembly code.
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*/
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class fs_generator
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{
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public:
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fs_generator(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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struct brw_stage_prog_data *prog_data,
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unsigned promoted_constants,
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bool runtime_check_aads_emit,
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gl_shader_stage stage);
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~fs_generator();
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void enable_debug(const char *shader_name);
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int generate_code(const cfg_t *cfg, int dispatch_width);
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const unsigned *get_assembly();
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private:
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void fire_fb_write(fs_inst *inst,
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struct brw_reg payload,
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struct brw_reg implied_header,
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GLuint nr);
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void generate_send(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg desc,
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struct brw_reg ex_desc,
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struct brw_reg payload,
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struct brw_reg payload2);
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void generate_fb_write(fs_inst *inst, struct brw_reg payload);
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void generate_fb_read(fs_inst *inst, struct brw_reg dst,
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struct brw_reg payload);
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void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
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void generate_urb_write(fs_inst *inst, struct brw_reg payload);
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void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
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void generate_barrier(fs_inst *inst, struct brw_reg src);
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bool generate_linterp(fs_inst *inst, struct brw_reg dst,
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struct brw_reg *src);
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void generate_tex(fs_inst *inst, struct brw_reg dst,
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struct brw_reg surface_index,
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struct brw_reg sampler_index);
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void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
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struct brw_reg src,
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struct brw_reg surf_index);
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void generate_ddx(const fs_inst *inst,
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struct brw_reg dst, struct brw_reg src);
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void generate_ddy(const fs_inst *inst,
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struct brw_reg dst, struct brw_reg src);
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void generate_scratch_write(fs_inst *inst, struct brw_reg src);
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void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
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void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
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void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
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struct brw_reg index,
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struct brw_reg offset);
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void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg surf_index,
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struct brw_reg payload);
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void generate_varying_pull_constant_load_gen4(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg index);
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void generate_mov_dispatch_to_flags(fs_inst *inst);
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void generate_pixel_interpolator_query(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg src,
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struct brw_reg msg_data,
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unsigned msg_type);
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void generate_set_sample_id(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1);
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void generate_discard_jump(fs_inst *inst);
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void generate_pack_half_2x16_split(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg x,
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struct brw_reg y);
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void generate_shader_time_add(fs_inst *inst,
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struct brw_reg payload,
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struct brw_reg offset,
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struct brw_reg value);
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void generate_mov_indirect(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg reg,
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struct brw_reg indirect_byte_offset);
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void generate_shuffle(fs_inst *inst,
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struct brw_reg dst,
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struct brw_reg src,
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struct brw_reg idx);
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void generate_quad_swizzle(const fs_inst *inst,
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struct brw_reg dst, struct brw_reg src,
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unsigned swiz);
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bool patch_discard_jumps_to_fb_writes();
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const struct brw_compiler *compiler;
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void *log_data; /* Passed to compiler->*_log functions */
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const struct gen_device_info *devinfo;
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struct brw_codegen *p;
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struct brw_stage_prog_data * const prog_data;
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unsigned dispatch_width; /**< 8, 16 or 32 */
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exec_list discard_halt_patches;
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unsigned promoted_constants;
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bool runtime_check_aads_emit;
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bool debug_flag;
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const char *shader_name;
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gl_shader_stage stage;
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void *mem_ctx;
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};
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namespace brw {
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inline fs_reg
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fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
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brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1)
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{
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if (!regs[0])
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return fs_reg();
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if (bld.dispatch_width() > 16) {
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const fs_reg tmp = bld.vgrf(type, n);
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const brw::fs_builder hbld = bld.exec_all().group(16, 0);
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const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
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fs_reg *const components = new fs_reg[n * m];
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for (unsigned c = 0; c < n; c++) {
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for (unsigned g = 0; g < m; g++) {
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components[c * m + g] =
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offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
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}
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}
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hbld.LOAD_PAYLOAD(tmp, components, n * m, 0);
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delete[] components;
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return tmp;
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} else {
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return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
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}
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}
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bool
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lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
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}
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void shuffle_from_32bit_read(const brw::fs_builder &bld,
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const fs_reg &dst,
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const fs_reg &src,
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uint32_t first_component,
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uint32_t components);
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fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld,
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const fs_reg &src,
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uint32_t first_component,
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uint32_t components);
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fs_reg setup_imm_df(const brw::fs_builder &bld,
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double v);
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fs_reg setup_imm_b(const brw::fs_builder &bld,
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int8_t v);
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fs_reg setup_imm_ub(const brw::fs_builder &bld,
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|
uint8_t v);
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enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
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nir_intrinsic_op op);
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#endif /* BRW_FS_H */
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