700bebb958
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
89 lines
3.2 KiB
C++
89 lines
3.2 KiB
C++
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* \file brw_vec4_tcs.h
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*
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* The vec4-mode tessellation control shader compiler backend.
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*/
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#ifndef BRW_VEC4_TCS_H
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#define BRW_VEC4_TCS_H
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#include "brw_compiler.h"
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#include "brw_vec4.h"
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#ifdef __cplusplus
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namespace brw {
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class vec4_tcs_visitor : public vec4_visitor
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{
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public:
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vec4_tcs_visitor(const struct brw_compiler *compiler,
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void *log_data,
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const struct brw_tcs_prog_key *key,
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struct brw_tcs_prog_data *prog_data,
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const nir_shader *nir,
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void *mem_ctx,
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int shader_time_index,
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const struct brw_vue_map *input_vue_map);
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protected:
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virtual dst_reg *make_reg_for_system_value(int location);
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virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
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virtual void setup_payload();
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virtual void emit_prolog();
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virtual void emit_thread_end();
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virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
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void emit_input_urb_read(const dst_reg &dst,
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const src_reg &vertex_index,
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unsigned base_offset,
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unsigned first_component,
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const src_reg &indirect_offset);
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void emit_output_urb_read(const dst_reg &dst,
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unsigned base_offset,
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unsigned first_component,
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const src_reg &indirect_offset);
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void emit_urb_write(const src_reg &value, unsigned writemask,
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unsigned base_offset, const src_reg &indirect_offset);
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/* we do not use the normal end-of-shader URB write mechanism -- but every vec4 stage
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* must provide implementations of these:
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*/
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virtual void emit_urb_write_header(int mrf) {}
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virtual vec4_instruction *emit_urb_write_opcode(bool complete) { return NULL; }
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const struct brw_vue_map *input_vue_map;
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const struct brw_tcs_prog_key *key;
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src_reg invocation_id;
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};
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} /* namespace brw */
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#endif /* __cplusplus */
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#endif /* BRW_VEC4_TCS_H */
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