9ee67467c9
When using DCC some clear values don't require a cmask eliminate step. This patch adds support for black and black with alpha 1, there are other values, but I don't have access to a comprehensive list. This works by setting the cmask eliminate predicate when doing the fast clear, and later when doing the cmask elimination making sure the draws are predicated. This increases the fps on Sascha Willems deferred. Tonga: 580fps->670fps on a Tonga PRO card. Polaris 730->850fps Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
1421 lines
48 KiB
C
1421 lines
48 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "nir/nir_builder.h"
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#include "util/format_rgb9e5.h"
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#include "vk_format.h"
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enum {
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DEPTH_CLEAR_SLOW,
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DEPTH_CLEAR_FAST_EXPCLEAR,
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DEPTH_CLEAR_FAST_NO_EXPCLEAR
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};
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static void
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build_color_shaders(struct nir_shader **out_vs,
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struct nir_shader **out_fs,
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uint32_t frag_output)
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{
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nir_builder vs_b;
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nir_builder fs_b;
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nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
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nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
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vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
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fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
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const struct glsl_type *position_type = glsl_vec4_type();
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const struct glsl_type *color_type = glsl_vec4_type();
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nir_variable *vs_out_pos =
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nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
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"gl_Position");
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vs_out_pos->data.location = VARYING_SLOT_POS;
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nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
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nir_intrinsic_set_base(in_color_load, 0);
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nir_intrinsic_set_range(in_color_load, 16);
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in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
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in_color_load->num_components = 4;
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nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
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nir_builder_instr_insert(&fs_b, &in_color_load->instr);
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nir_variable *fs_out_color =
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nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
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"f_color");
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fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
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nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
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nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
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nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
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const struct glsl_type *layer_type = glsl_int_type();
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nir_variable *vs_out_layer =
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nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
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"v_layer");
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vs_out_layer->data.location = VARYING_SLOT_LAYER;
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vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
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nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
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nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
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*out_vs = vs_b.shader;
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*out_fs = fs_b.shader;
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}
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static VkResult
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create_pipeline(struct radv_device *device,
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struct radv_render_pass *render_pass,
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uint32_t samples,
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struct nir_shader *vs_nir,
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struct nir_shader *fs_nir,
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const VkPipelineVertexInputStateCreateInfo *vi_state,
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const VkPipelineDepthStencilStateCreateInfo *ds_state,
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const VkPipelineColorBlendStateCreateInfo *cb_state,
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const VkPipelineLayout layout,
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const struct radv_graphics_pipeline_create_info *extra,
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const VkAllocationCallbacks *alloc,
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struct radv_pipeline **pipeline)
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{
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VkDevice device_h = radv_device_to_handle(device);
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VkResult result;
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struct radv_shader_module vs_m = { .nir = vs_nir };
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struct radv_shader_module fs_m = { .nir = fs_nir };
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VkPipeline pipeline_h = VK_NULL_HANDLE;
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result = radv_graphics_pipeline_create(device_h,
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&(VkGraphicsPipelineCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.stageCount = fs_nir ? 2 : 1,
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.pStages = (VkPipelineShaderStageCreateInfo[]) {
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = radv_shader_module_to_handle(&vs_m),
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.pName = "main",
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},
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = radv_shader_module_to_handle(&fs_m),
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.pName = "main",
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},
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},
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.pVertexInputState = vi_state,
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.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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},
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.pViewportState = &(VkPipelineViewportStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
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.depthBiasEnable = false,
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},
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.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = samples,
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.sampleShadingEnable = false,
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.pSampleMask = NULL,
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.alphaToCoverageEnable = false,
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.alphaToOneEnable = false,
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},
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.pDepthStencilState = ds_state,
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.pColorBlendState = cb_state,
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.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
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/* The meta clear pipeline declares all state as dynamic.
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* As a consequence, vkCmdBindPipeline writes no dynamic state
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* to the cmd buffer. Therefore, at the end of the meta clear,
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* we need only restore dynamic state was vkCmdSet.
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*/
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 8,
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.pDynamicStates = (VkDynamicState[]) {
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/* Everything except stencil write mask */
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_LINE_WIDTH,
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VK_DYNAMIC_STATE_DEPTH_BIAS,
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VK_DYNAMIC_STATE_BLEND_CONSTANTS,
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VK_DYNAMIC_STATE_DEPTH_BOUNDS,
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VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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VK_DYNAMIC_STATE_STENCIL_REFERENCE,
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},
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},
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.layout = layout,
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.flags = 0,
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.renderPass = radv_render_pass_to_handle(render_pass),
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.subpass = 0,
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},
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extra,
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alloc,
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&pipeline_h);
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ralloc_free(vs_nir);
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ralloc_free(fs_nir);
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*pipeline = radv_pipeline_from_handle(pipeline_h);
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return result;
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}
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static VkResult
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create_color_renderpass(struct radv_device *device,
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VkFormat vk_format,
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uint32_t samples,
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VkRenderPass *pass)
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{
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return radv_CreateRenderPass(radv_device_to_handle(device),
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&(VkRenderPassCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
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.attachmentCount = 1,
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.pAttachments = &(VkAttachmentDescription) {
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.format = vk_format,
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.samples = samples,
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.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
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.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
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.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
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.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.subpassCount = 1,
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.pSubpasses = &(VkSubpassDescription) {
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.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
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.inputAttachmentCount = 0,
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.colorAttachmentCount = 1,
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.pColorAttachments = &(VkAttachmentReference) {
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.attachment = 0,
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.layout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.pResolveAttachments = NULL,
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.pDepthStencilAttachment = &(VkAttachmentReference) {
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.attachment = VK_ATTACHMENT_UNUSED,
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.layout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.preserveAttachmentCount = 1,
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.pPreserveAttachments = (uint32_t[]) { 0 },
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},
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.dependencyCount = 0,
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}, &device->meta_state.alloc, pass);
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}
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static VkResult
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create_color_pipeline(struct radv_device *device,
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uint32_t samples,
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uint32_t frag_output,
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struct radv_pipeline **pipeline,
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VkRenderPass pass)
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{
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struct nir_shader *vs_nir;
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struct nir_shader *fs_nir;
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VkResult result;
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build_color_shaders(&vs_nir, &fs_nir, frag_output);
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const VkPipelineVertexInputStateCreateInfo vi_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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.vertexBindingDescriptionCount = 0,
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.vertexAttributeDescriptionCount = 0,
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};
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const VkPipelineDepthStencilStateCreateInfo ds_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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.depthTestEnable = false,
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.depthWriteEnable = false,
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.depthBoundsTestEnable = false,
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.stencilTestEnable = false,
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};
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VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
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blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
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.blendEnable = false,
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.colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
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VK_COLOR_COMPONENT_R_BIT |
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VK_COLOR_COMPONENT_G_BIT |
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VK_COLOR_COMPONENT_B_BIT,
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};
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const VkPipelineColorBlendStateCreateInfo cb_state = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.logicOpEnable = false,
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.attachmentCount = MAX_RTS,
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.pAttachments = blend_attachment_state
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};
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struct radv_graphics_pipeline_create_info extra = {
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.use_rectlist = true,
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};
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result = create_pipeline(device, radv_render_pass_from_handle(pass),
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samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
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device->meta_state.clear_color_p_layout,
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&extra, &device->meta_state.alloc, pipeline);
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return result;
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}
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static void
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destroy_pipeline(struct radv_device *device, struct radv_pipeline *pipeline)
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{
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if (!pipeline)
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return;
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radv_DestroyPipeline(radv_device_to_handle(device),
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radv_pipeline_to_handle(pipeline),
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&device->meta_state.alloc);
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}
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static void
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destroy_render_pass(struct radv_device *device, VkRenderPass renderpass)
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{
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radv_DestroyRenderPass(radv_device_to_handle(device), renderpass,
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&device->meta_state.alloc);
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}
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void
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radv_device_finish_meta_clear_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
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for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
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destroy_pipeline(device, state->clear[i].color_pipelines[j]);
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destroy_render_pass(device, state->clear[i].render_pass[j]);
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}
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for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
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destroy_pipeline(device, state->clear[i].depth_only_pipeline[j]);
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destroy_pipeline(device, state->clear[i].stencil_only_pipeline[j]);
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destroy_pipeline(device, state->clear[i].depthstencil_pipeline[j]);
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}
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destroy_render_pass(device, state->clear[i].depthstencil_rp);
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}
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->clear_color_p_layout,
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&state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->clear_depth_p_layout,
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&state->alloc);
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}
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static void
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emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
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const VkClearAttachment *clear_att,
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const VkClearRect *clear_rect)
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{
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struct radv_device *device = cmd_buffer->device;
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const struct radv_subpass *subpass = cmd_buffer->state.subpass;
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const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
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const uint32_t subpass_att = clear_att->colorAttachment;
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const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
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const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
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const uint32_t samples = iview->image->info.samples;
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const uint32_t samples_log2 = ffs(samples) - 1;
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unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
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struct radv_pipeline *pipeline;
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VkClearColorValue clear_value = clear_att->clearValue.color;
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VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
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VkPipeline pipeline_h;
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if (fs_key == -1) {
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radv_finishme("color clears incomplete");
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return;
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}
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pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
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pipeline_h = radv_pipeline_to_handle(pipeline);
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if (!pipeline) {
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radv_finishme("color clears incomplete");
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return;
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}
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assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
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assert(pipeline);
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assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
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assert(clear_att->colorAttachment < subpass->color_count);
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.clear_color_p_layout,
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VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
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&clear_value);
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struct radv_subpass clear_subpass = {
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.color_count = 1,
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.color_attachments = (VkAttachmentReference[]) {
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subpass->color_attachments[clear_att->colorAttachment]
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},
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.depth_stencil_attachment = (VkAttachmentReference) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
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};
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radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
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if (cmd_buffer->state.pipeline != pipeline) {
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radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
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pipeline_h);
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}
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radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
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.x = clear_rect->rect.offset.x,
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.y = clear_rect->rect.offset.y,
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.width = clear_rect->rect.extent.width,
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.height = clear_rect->rect.extent.height,
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.minDepth = 0.0f,
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.maxDepth = 1.0f
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});
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radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
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radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
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radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
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}
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static void
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build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
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{
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nir_builder vs_b, fs_b;
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nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
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nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
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vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
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fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
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const struct glsl_type *position_out_type = glsl_vec4_type();
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|
|
nir_variable *vs_out_pos =
|
|
nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
|
|
"gl_Position");
|
|
vs_out_pos->data.location = VARYING_SLOT_POS;
|
|
|
|
nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
|
|
nir_intrinsic_set_base(in_color_load, 0);
|
|
nir_intrinsic_set_range(in_color_load, 4);
|
|
in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
|
|
in_color_load->num_components = 1;
|
|
nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
|
|
nir_builder_instr_insert(&vs_b, &in_color_load->instr);
|
|
|
|
nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
|
|
nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
|
|
|
|
const struct glsl_type *layer_type = glsl_int_type();
|
|
nir_variable *vs_out_layer =
|
|
nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
|
|
"v_layer");
|
|
vs_out_layer->data.location = VARYING_SLOT_LAYER;
|
|
vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
|
|
nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
|
|
nir_store_var(&vs_b, vs_out_layer, inst_id, 0x1);
|
|
|
|
*out_vs = vs_b.shader;
|
|
*out_fs = fs_b.shader;
|
|
}
|
|
|
|
static VkResult
|
|
create_depthstencil_renderpass(struct radv_device *device,
|
|
uint32_t samples,
|
|
VkRenderPass *render_pass)
|
|
{
|
|
return radv_CreateRenderPass(radv_device_to_handle(device),
|
|
&(VkRenderPassCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
|
|
.attachmentCount = 1,
|
|
.pAttachments = &(VkAttachmentDescription) {
|
|
.format = VK_FORMAT_D32_SFLOAT_S8_UINT,
|
|
.samples = samples,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
.subpassCount = 1,
|
|
.pSubpasses = &(VkSubpassDescription) {
|
|
.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
.inputAttachmentCount = 0,
|
|
.colorAttachmentCount = 0,
|
|
.pColorAttachments = NULL,
|
|
.pResolveAttachments = NULL,
|
|
.pDepthStencilAttachment = &(VkAttachmentReference) {
|
|
.attachment = 0,
|
|
.layout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
.preserveAttachmentCount = 1,
|
|
.pPreserveAttachments = (uint32_t[]) { 0 },
|
|
},
|
|
.dependencyCount = 0,
|
|
}, &device->meta_state.alloc, render_pass);
|
|
}
|
|
|
|
static VkResult
|
|
create_depthstencil_pipeline(struct radv_device *device,
|
|
VkImageAspectFlags aspects,
|
|
uint32_t samples,
|
|
int index,
|
|
struct radv_pipeline **pipeline,
|
|
VkRenderPass render_pass)
|
|
{
|
|
struct nir_shader *vs_nir, *fs_nir;
|
|
VkResult result;
|
|
build_depthstencil_shader(&vs_nir, &fs_nir);
|
|
|
|
const VkPipelineVertexInputStateCreateInfo vi_state = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
|
|
.vertexBindingDescriptionCount = 0,
|
|
.vertexAttributeDescriptionCount = 0,
|
|
};
|
|
|
|
const VkPipelineDepthStencilStateCreateInfo ds_state = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
|
|
.depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
|
|
.depthCompareOp = VK_COMPARE_OP_ALWAYS,
|
|
.depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
|
|
.depthBoundsTestEnable = false,
|
|
.stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
|
|
.front = {
|
|
.passOp = VK_STENCIL_OP_REPLACE,
|
|
.compareOp = VK_COMPARE_OP_ALWAYS,
|
|
.writeMask = UINT32_MAX,
|
|
.reference = 0, /* dynamic */
|
|
},
|
|
.back = { 0 /* dont care */ },
|
|
};
|
|
|
|
const VkPipelineColorBlendStateCreateInfo cb_state = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
|
|
.logicOpEnable = false,
|
|
.attachmentCount = 0,
|
|
.pAttachments = NULL,
|
|
};
|
|
|
|
struct radv_graphics_pipeline_create_info extra = {
|
|
.use_rectlist = true,
|
|
};
|
|
|
|
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
|
|
extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
|
|
extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
|
|
}
|
|
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
|
|
extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
|
|
extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
|
|
}
|
|
result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
|
|
samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
|
|
device->meta_state.clear_depth_p_layout,
|
|
&extra, &device->meta_state.alloc, pipeline);
|
|
return result;
|
|
}
|
|
|
|
static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
|
|
const struct radv_image_view *iview,
|
|
VkImageLayout layout,
|
|
const VkClearRect *clear_rect)
|
|
{
|
|
uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
|
|
cmd_buffer->queue_family_index,
|
|
cmd_buffer->queue_family_index);
|
|
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
|
|
clear_rect->rect.extent.width != iview->extent.width ||
|
|
clear_rect->rect.extent.height != iview->extent.height)
|
|
return false;
|
|
if (iview->image->surface.htile_size &&
|
|
iview->base_mip == 0 &&
|
|
iview->base_layer == 0 &&
|
|
radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
|
|
!radv_image_extent_compare(iview->image, &iview->extent))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static struct radv_pipeline *
|
|
pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_meta_state *meta_state,
|
|
const struct radv_image_view *iview,
|
|
int samples_log2,
|
|
VkImageAspectFlags aspects,
|
|
VkImageLayout layout,
|
|
const VkClearRect *clear_rect,
|
|
VkClearDepthStencilValue clear_value)
|
|
{
|
|
bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
|
|
int index = DEPTH_CLEAR_SLOW;
|
|
|
|
if (fast) {
|
|
/* we don't know the previous clear values, so we always have
|
|
* the NO_EXPCLEAR path */
|
|
index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
|
|
}
|
|
|
|
switch (aspects) {
|
|
case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
|
|
return meta_state->clear[samples_log2].depthstencil_pipeline[index];
|
|
case VK_IMAGE_ASPECT_DEPTH_BIT:
|
|
return meta_state->clear[samples_log2].depth_only_pipeline[index];
|
|
case VK_IMAGE_ASPECT_STENCIL_BIT:
|
|
return meta_state->clear[samples_log2].stencil_only_pipeline[index];
|
|
}
|
|
unreachable("expected depth or stencil aspect");
|
|
}
|
|
|
|
static void
|
|
emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
|
|
const VkClearAttachment *clear_att,
|
|
const VkClearRect *clear_rect)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
struct radv_meta_state *meta_state = &device->meta_state;
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
|
|
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
|
|
VkImageAspectFlags aspects = clear_att->aspectMask;
|
|
const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
|
|
const uint32_t samples = iview->image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
|
|
|
|
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT ||
|
|
aspects == VK_IMAGE_ASPECT_STENCIL_BIT ||
|
|
aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
|
|
VK_IMAGE_ASPECT_STENCIL_BIT));
|
|
assert(pass_att != VK_ATTACHMENT_UNUSED);
|
|
|
|
if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
|
|
clear_value.depth = 1.0f;
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
device->meta_state.clear_depth_p_layout,
|
|
VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
|
|
&clear_value.depth);
|
|
|
|
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
|
|
radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
|
|
clear_value.stencil);
|
|
}
|
|
|
|
struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
|
|
meta_state,
|
|
iview,
|
|
samples_log2,
|
|
aspects,
|
|
subpass->depth_stencil_attachment.layout,
|
|
clear_rect,
|
|
clear_value);
|
|
if (cmd_buffer->state.pipeline != pipeline) {
|
|
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
radv_pipeline_to_handle(pipeline));
|
|
}
|
|
|
|
if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
|
|
radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
|
|
.x = clear_rect->rect.offset.x,
|
|
.y = clear_rect->rect.offset.y,
|
|
.width = clear_rect->rect.extent.width,
|
|
.height = clear_rect->rect.extent.height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f
|
|
});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
|
|
|
|
radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, 0);
|
|
}
|
|
|
|
static bool
|
|
emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
|
|
const VkClearAttachment *clear_att,
|
|
const VkClearRect *clear_rect,
|
|
enum radv_cmd_flush_bits *pre_flush,
|
|
enum radv_cmd_flush_bits *post_flush)
|
|
{
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
|
|
VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
|
|
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
|
|
VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
|
|
VkImageAspectFlags aspects = clear_att->aspectMask;
|
|
uint32_t clear_word;
|
|
|
|
if (!iview->image->surface.htile_size)
|
|
return false;
|
|
|
|
if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
|
|
return false;
|
|
|
|
if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
|
|
goto fail;
|
|
|
|
/* don't fast clear 3D */
|
|
if (iview->image->type == VK_IMAGE_TYPE_3D)
|
|
goto fail;
|
|
|
|
/* all layers are bound */
|
|
if (iview->base_layer > 0)
|
|
goto fail;
|
|
if (iview->image->info.array_size != iview->layer_count)
|
|
goto fail;
|
|
|
|
if (iview->image->info.levels > 1)
|
|
goto fail;
|
|
|
|
if (!radv_image_extent_compare(iview->image, &iview->extent))
|
|
goto fail;
|
|
|
|
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
|
|
clear_rect->rect.extent.width != iview->image->info.width ||
|
|
clear_rect->rect.extent.height != iview->image->info.height)
|
|
goto fail;
|
|
|
|
if (clear_rect->baseArrayLayer != 0)
|
|
goto fail;
|
|
if (clear_rect->layerCount != iview->image->info.array_size)
|
|
goto fail;
|
|
|
|
if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
|
|
goto fail;
|
|
|
|
if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
|
|
if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
|
|
goto fail;
|
|
clear_word = clear_value.depth ? 0xfffc0000 : 0;
|
|
} else
|
|
clear_word = clear_value.depth ? 0xfffffff0 : 0;
|
|
|
|
if (pre_flush) {
|
|
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
|
|
*pre_flush |= cmd_buffer->state.flush_bits;
|
|
} else
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
|
|
|
|
radv_fill_buffer(cmd_buffer, iview->image->bo,
|
|
iview->image->offset + iview->image->htile_offset,
|
|
iview->image->surface.htile_size, clear_word);
|
|
|
|
|
|
radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
|
|
if (post_flush)
|
|
*post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
|
|
RADV_CMD_FLAG_INV_VMEM_L1 |
|
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
|
|
else
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
|
|
RADV_CMD_FLAG_INV_VMEM_L1 |
|
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
|
|
return true;
|
|
fail:
|
|
return false;
|
|
}
|
|
|
|
static VkFormat pipeline_formats[] = {
|
|
VK_FORMAT_R8G8B8A8_UNORM,
|
|
VK_FORMAT_R8G8B8A8_UINT,
|
|
VK_FORMAT_R8G8B8A8_SINT,
|
|
VK_FORMAT_R16G16B16A16_UNORM,
|
|
VK_FORMAT_R16G16B16A16_SNORM,
|
|
VK_FORMAT_R16G16B16A16_UINT,
|
|
VK_FORMAT_R16G16B16A16_SINT,
|
|
VK_FORMAT_R32_SFLOAT,
|
|
VK_FORMAT_R32G32_SFLOAT,
|
|
VK_FORMAT_R32G32B32A32_SFLOAT
|
|
};
|
|
|
|
VkResult
|
|
radv_device_init_meta_clear_state(struct radv_device *device)
|
|
{
|
|
VkResult res;
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
memset(&device->meta_state.clear, 0, sizeof(device->meta_state.clear));
|
|
|
|
VkPipelineLayoutCreateInfo pl_color_create_info = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
.setLayoutCount = 0,
|
|
.pushConstantRangeCount = 1,
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
|
|
};
|
|
|
|
res = radv_CreatePipelineLayout(radv_device_to_handle(device),
|
|
&pl_color_create_info,
|
|
&device->meta_state.alloc,
|
|
&device->meta_state.clear_color_p_layout);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
VkPipelineLayoutCreateInfo pl_depth_create_info = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
.setLayoutCount = 0,
|
|
.pushConstantRangeCount = 1,
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
|
|
};
|
|
|
|
res = radv_CreatePipelineLayout(radv_device_to_handle(device),
|
|
&pl_depth_create_info,
|
|
&device->meta_state.alloc,
|
|
&device->meta_state.clear_depth_p_layout);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
|
|
uint32_t samples = 1 << i;
|
|
for (uint32_t j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
|
|
VkFormat format = pipeline_formats[j];
|
|
unsigned fs_key = radv_format_meta_fs_key(format);
|
|
assert(!state->clear[i].color_pipelines[fs_key]);
|
|
|
|
res = create_color_renderpass(device, format, samples,
|
|
&state->clear[i].render_pass[fs_key]);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
|
|
state->clear[i].render_pass[fs_key]);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
}
|
|
|
|
res = create_depthstencil_renderpass(device,
|
|
samples,
|
|
&state->clear[i].depthstencil_rp);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
|
|
res = create_depthstencil_pipeline(device,
|
|
VK_IMAGE_ASPECT_DEPTH_BIT,
|
|
samples,
|
|
j,
|
|
&state->clear[i].depth_only_pipeline[j],
|
|
state->clear[i].depthstencil_rp);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depthstencil_pipeline(device,
|
|
VK_IMAGE_ASPECT_STENCIL_BIT,
|
|
samples,
|
|
j,
|
|
&state->clear[i].stencil_only_pipeline[j],
|
|
state->clear[i].depthstencil_rp);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depthstencil_pipeline(device,
|
|
VK_IMAGE_ASPECT_DEPTH_BIT |
|
|
VK_IMAGE_ASPECT_STENCIL_BIT,
|
|
samples,
|
|
j,
|
|
&state->clear[i].depthstencil_pipeline[j],
|
|
state->clear[i].depthstencil_rp);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
}
|
|
}
|
|
return VK_SUCCESS;
|
|
|
|
fail:
|
|
radv_device_finish_meta_clear_state(device);
|
|
return res;
|
|
}
|
|
|
|
static void vi_get_fast_clear_parameters(VkFormat format,
|
|
const VkClearColorValue *clear_value,
|
|
uint32_t* reset_value,
|
|
bool *can_avoid_fast_clear_elim)
|
|
{
|
|
bool values[4] = {};
|
|
int extra_channel;
|
|
bool main_value = false;
|
|
bool extra_value = false;
|
|
int i;
|
|
*can_avoid_fast_clear_elim = false;
|
|
|
|
*reset_value = 0x20202020U;
|
|
|
|
const struct vk_format_description *desc = vk_format_description(format);
|
|
if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
|
|
format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
|
|
format == VK_FORMAT_B5G6R5_UNORM_PACK16)
|
|
extra_channel = -1;
|
|
else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
|
|
if (radv_translate_colorswap(format, false) <= 1)
|
|
extra_channel = desc->nr_channels - 1;
|
|
else
|
|
extra_channel = 0;
|
|
} else
|
|
return;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
int index = desc->swizzle[i] - VK_SWIZZLE_X;
|
|
if (desc->swizzle[i] < VK_SWIZZLE_X ||
|
|
desc->swizzle[i] > VK_SWIZZLE_W)
|
|
continue;
|
|
|
|
if (desc->channel[i].pure_integer &&
|
|
desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
|
|
/* Use the maximum value for clamping the clear color. */
|
|
int max = u_bit_consecutive(0, desc->channel[i].size - 1);
|
|
|
|
values[i] = clear_value->int32[i] != 0;
|
|
if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
|
|
return;
|
|
} else if (desc->channel[i].pure_integer &&
|
|
desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
|
|
/* Use the maximum value for clamping the clear color. */
|
|
unsigned max = u_bit_consecutive(0, desc->channel[i].size);
|
|
|
|
values[i] = clear_value->uint32[i] != 0U;
|
|
if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
|
|
return;
|
|
} else {
|
|
values[i] = clear_value->float32[i] != 0.0F;
|
|
if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
|
|
return;
|
|
}
|
|
|
|
if (index == extra_channel)
|
|
extra_value = values[i];
|
|
else
|
|
main_value = values[i];
|
|
}
|
|
|
|
for (int i = 0; i < 4; ++i)
|
|
if (values[i] != main_value &&
|
|
desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
|
|
desc->swizzle[i] >= VK_SWIZZLE_X &&
|
|
desc->swizzle[i] <= VK_SWIZZLE_W)
|
|
return;
|
|
|
|
*can_avoid_fast_clear_elim = true;
|
|
if (main_value)
|
|
*reset_value |= 0x80808080U;
|
|
|
|
if (extra_value)
|
|
*reset_value |= 0x40404040U;
|
|
return;
|
|
}
|
|
|
|
static bool
|
|
emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
|
|
const VkClearAttachment *clear_att,
|
|
const VkClearRect *clear_rect,
|
|
enum radv_cmd_flush_bits *pre_flush,
|
|
enum radv_cmd_flush_bits *post_flush)
|
|
{
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
const uint32_t subpass_att = clear_att->colorAttachment;
|
|
const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
|
|
VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
|
|
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const struct radv_image_view *iview = fb->attachments[pass_att].attachment;
|
|
VkClearColorValue clear_value = clear_att->clearValue.color;
|
|
uint32_t clear_color[2];
|
|
bool ret;
|
|
|
|
if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
|
|
return false;
|
|
|
|
if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
|
|
return false;
|
|
|
|
if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
|
|
goto fail;
|
|
|
|
/* don't fast clear 3D */
|
|
if (iview->image->type == VK_IMAGE_TYPE_3D)
|
|
goto fail;
|
|
|
|
/* all layers are bound */
|
|
if (iview->base_layer > 0)
|
|
goto fail;
|
|
if (iview->image->info.array_size != iview->layer_count)
|
|
goto fail;
|
|
|
|
if (iview->image->info.levels > 1)
|
|
goto fail;
|
|
|
|
if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
|
|
goto fail;
|
|
if (!radv_image_extent_compare(iview->image, &iview->extent))
|
|
goto fail;
|
|
|
|
if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
|
|
clear_rect->rect.extent.width != iview->image->info.width ||
|
|
clear_rect->rect.extent.height != iview->image->info.height)
|
|
goto fail;
|
|
|
|
if (clear_rect->baseArrayLayer != 0)
|
|
goto fail;
|
|
if (clear_rect->layerCount != iview->image->info.array_size)
|
|
goto fail;
|
|
|
|
/* RB+ doesn't work with CMASK fast clear on Stoney. */
|
|
if (!iview->image->surface.dcc_size &&
|
|
cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
|
|
goto fail;
|
|
|
|
/* DCC */
|
|
ret = radv_format_pack_clear_color(iview->image->vk_format,
|
|
clear_color, &clear_value);
|
|
if (ret == false)
|
|
goto fail;
|
|
|
|
if (pre_flush) {
|
|
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
|
|
*pre_flush |= cmd_buffer->state.flush_bits;
|
|
} else
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
|
|
/* clear cmask buffer */
|
|
if (iview->image->surface.dcc_size) {
|
|
uint32_t reset_value;
|
|
bool can_avoid_fast_clear_elim;
|
|
vi_get_fast_clear_parameters(iview->image->vk_format,
|
|
&clear_value, &reset_value,
|
|
&can_avoid_fast_clear_elim);
|
|
|
|
radv_fill_buffer(cmd_buffer, iview->image->bo,
|
|
iview->image->offset + iview->image->dcc_offset,
|
|
iview->image->surface.dcc_size, reset_value);
|
|
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
|
|
!can_avoid_fast_clear_elim);
|
|
} else {
|
|
|
|
if (iview->image->surface.bpe > 8) {
|
|
/* 128 bit formats not supported */
|
|
return false;
|
|
}
|
|
radv_fill_buffer(cmd_buffer, iview->image->bo,
|
|
iview->image->offset + iview->image->cmask.offset,
|
|
iview->image->cmask.size, 0);
|
|
}
|
|
|
|
if (post_flush)
|
|
*post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
|
|
RADV_CMD_FLAG_INV_VMEM_L1 |
|
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
|
|
else
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
|
|
RADV_CMD_FLAG_INV_VMEM_L1 |
|
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
|
|
|
|
radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color);
|
|
|
|
return true;
|
|
fail:
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* The parameters mean that same as those in vkCmdClearAttachments.
|
|
*/
|
|
static void
|
|
emit_clear(struct radv_cmd_buffer *cmd_buffer,
|
|
const VkClearAttachment *clear_att,
|
|
const VkClearRect *clear_rect,
|
|
enum radv_cmd_flush_bits *pre_flush,
|
|
enum radv_cmd_flush_bits *post_flush)
|
|
{
|
|
if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
|
|
|
|
if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
|
|
pre_flush, post_flush))
|
|
emit_color_clear(cmd_buffer, clear_att, clear_rect);
|
|
} else {
|
|
assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
|
|
VK_IMAGE_ASPECT_STENCIL_BIT));
|
|
if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
|
|
pre_flush, post_flush))
|
|
emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
|
|
}
|
|
}
|
|
|
|
static bool
|
|
subpass_needs_clear(const struct radv_cmd_buffer *cmd_buffer)
|
|
{
|
|
const struct radv_cmd_state *cmd_state = &cmd_buffer->state;
|
|
uint32_t ds;
|
|
|
|
if (!cmd_state->subpass)
|
|
return false;
|
|
ds = cmd_state->subpass->depth_stencil_attachment.attachment;
|
|
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
|
|
uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
|
|
if (cmd_state->attachments[a].pending_clear_aspects) {
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (ds != VK_ATTACHMENT_UNUSED &&
|
|
cmd_state->attachments[ds].pending_clear_aspects) {
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* Emit any pending attachment clears for the current subpass.
|
|
*
|
|
* @see radv_attachment_state::pending_clear_aspects
|
|
*/
|
|
void
|
|
radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
|
|
{
|
|
struct radv_cmd_state *cmd_state = &cmd_buffer->state;
|
|
struct radv_meta_saved_state saved_state;
|
|
enum radv_cmd_flush_bits pre_flush = 0;
|
|
enum radv_cmd_flush_bits post_flush = 0;
|
|
|
|
if (!subpass_needs_clear(cmd_buffer))
|
|
return;
|
|
|
|
radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
|
|
|
|
VkClearRect clear_rect = {
|
|
.rect = cmd_state->render_area,
|
|
.baseArrayLayer = 0,
|
|
.layerCount = cmd_state->framebuffer->layers,
|
|
};
|
|
|
|
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
|
|
uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
|
|
|
|
if (!cmd_state->attachments[a].pending_clear_aspects)
|
|
continue;
|
|
|
|
assert(cmd_state->attachments[a].pending_clear_aspects ==
|
|
VK_IMAGE_ASPECT_COLOR_BIT);
|
|
|
|
VkClearAttachment clear_att = {
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.colorAttachment = i, /* Use attachment index relative to subpass */
|
|
.clearValue = cmd_state->attachments[a].clear_value,
|
|
};
|
|
|
|
emit_clear(cmd_buffer, &clear_att, &clear_rect, &pre_flush, &post_flush);
|
|
cmd_state->attachments[a].pending_clear_aspects = 0;
|
|
}
|
|
|
|
uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
|
|
|
|
if (ds != VK_ATTACHMENT_UNUSED) {
|
|
|
|
if (cmd_state->attachments[ds].pending_clear_aspects) {
|
|
|
|
VkClearAttachment clear_att = {
|
|
.aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
|
|
.clearValue = cmd_state->attachments[ds].clear_value,
|
|
};
|
|
|
|
emit_clear(cmd_buffer, &clear_att, &clear_rect,
|
|
&pre_flush, &post_flush);
|
|
cmd_state->attachments[ds].pending_clear_aspects = 0;
|
|
}
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
cmd_buffer->state.flush_bits |= post_flush;
|
|
}
|
|
|
|
static void
|
|
radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image *image,
|
|
VkImageLayout image_layout,
|
|
const VkImageSubresourceRange *range,
|
|
VkFormat format, int level, int layer,
|
|
const VkClearValue *clear_val)
|
|
{
|
|
VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
|
|
struct radv_image_view iview;
|
|
radv_image_view_init(&iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(image),
|
|
.viewType = radv_meta_get_view_type(image),
|
|
.format = format,
|
|
.subresourceRange = {
|
|
.aspectMask = range->aspectMask,
|
|
.baseMipLevel = range->baseMipLevel + level,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = range->baseArrayLayer + layer,
|
|
.layerCount = 1
|
|
},
|
|
});
|
|
|
|
VkFramebuffer fb;
|
|
radv_CreateFramebuffer(device_h,
|
|
&(VkFramebufferCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
|
|
.attachmentCount = 1,
|
|
.pAttachments = (VkImageView[]) {
|
|
radv_image_view_to_handle(&iview),
|
|
},
|
|
.width = iview.extent.width,
|
|
.height = iview.extent.height,
|
|
.layers = 1
|
|
},
|
|
&cmd_buffer->pool->alloc,
|
|
&fb);
|
|
|
|
VkAttachmentDescription att_desc = {
|
|
.format = iview.vk_format,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
.initialLayout = image_layout,
|
|
.finalLayout = image_layout,
|
|
};
|
|
|
|
VkSubpassDescription subpass_desc = {
|
|
.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
.inputAttachmentCount = 0,
|
|
.colorAttachmentCount = 0,
|
|
.pColorAttachments = NULL,
|
|
.pResolveAttachments = NULL,
|
|
.pDepthStencilAttachment = NULL,
|
|
.preserveAttachmentCount = 0,
|
|
.pPreserveAttachments = NULL,
|
|
};
|
|
|
|
const VkAttachmentReference att_ref = {
|
|
.attachment = 0,
|
|
.layout = image_layout,
|
|
};
|
|
|
|
if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
|
|
subpass_desc.colorAttachmentCount = 1;
|
|
subpass_desc.pColorAttachments = &att_ref;
|
|
} else {
|
|
subpass_desc.pDepthStencilAttachment = &att_ref;
|
|
}
|
|
|
|
VkRenderPass pass;
|
|
radv_CreateRenderPass(device_h,
|
|
&(VkRenderPassCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
|
|
.attachmentCount = 1,
|
|
.pAttachments = &att_desc,
|
|
.subpassCount = 1,
|
|
.pSubpasses = &subpass_desc,
|
|
},
|
|
&cmd_buffer->pool->alloc,
|
|
&pass);
|
|
|
|
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
&(VkRenderPassBeginInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
|
|
.renderArea = {
|
|
.offset = { 0, 0, },
|
|
.extent = {
|
|
.width = iview.extent.width,
|
|
.height = iview.extent.height,
|
|
},
|
|
},
|
|
.renderPass = pass,
|
|
.framebuffer = fb,
|
|
.clearValueCount = 0,
|
|
.pClearValues = NULL,
|
|
},
|
|
VK_SUBPASS_CONTENTS_INLINE);
|
|
|
|
VkClearAttachment clear_att = {
|
|
.aspectMask = range->aspectMask,
|
|
.colorAttachment = 0,
|
|
.clearValue = *clear_val,
|
|
};
|
|
|
|
VkClearRect clear_rect = {
|
|
.rect = {
|
|
.offset = { 0, 0 },
|
|
.extent = { iview.extent.width, iview.extent.height },
|
|
},
|
|
.baseArrayLayer = range->baseArrayLayer,
|
|
.layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
|
|
};
|
|
|
|
emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL);
|
|
|
|
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
radv_DestroyRenderPass(device_h, pass,
|
|
&cmd_buffer->pool->alloc);
|
|
radv_DestroyFramebuffer(device_h, fb,
|
|
&cmd_buffer->pool->alloc);
|
|
}
|
|
static void
|
|
radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image *image,
|
|
VkImageLayout image_layout,
|
|
const VkClearValue *clear_value,
|
|
uint32_t range_count,
|
|
const VkImageSubresourceRange *ranges,
|
|
bool cs)
|
|
{
|
|
VkFormat format = image->vk_format;
|
|
VkClearValue internal_clear_value = *clear_value;
|
|
|
|
if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
|
|
uint32_t value;
|
|
format = VK_FORMAT_R32_UINT;
|
|
value = float3_to_rgb9e5(clear_value->color.float32);
|
|
internal_clear_value.color.uint32[0] = value;
|
|
}
|
|
|
|
if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
|
|
uint8_t r, g;
|
|
format = VK_FORMAT_R8_UINT;
|
|
r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
|
|
g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
|
|
internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
|
|
}
|
|
|
|
for (uint32_t r = 0; r < range_count; r++) {
|
|
const VkImageSubresourceRange *range = &ranges[r];
|
|
for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
|
|
const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
|
|
radv_minify(image->info.depth, range->baseMipLevel + l) :
|
|
radv_get_layerCount(image, range);
|
|
for (uint32_t s = 0; s < layer_count; ++s) {
|
|
|
|
if (cs) {
|
|
struct radv_meta_blit2d_surf surf;
|
|
surf.format = format;
|
|
surf.image = image;
|
|
surf.level = range->baseMipLevel + l;
|
|
surf.layer = range->baseArrayLayer + s;
|
|
surf.aspect_mask = range->aspectMask;
|
|
radv_meta_clear_image_cs(cmd_buffer, &surf,
|
|
&internal_clear_value.color);
|
|
} else {
|
|
radv_clear_image_layer(cmd_buffer, image, image_layout,
|
|
range, format, l, s, &internal_clear_value);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
union meta_saved_state {
|
|
struct radv_meta_saved_state gfx;
|
|
struct radv_meta_saved_compute_state compute;
|
|
};
|
|
|
|
void radv_CmdClearColorImage(
|
|
VkCommandBuffer commandBuffer,
|
|
VkImage image_h,
|
|
VkImageLayout imageLayout,
|
|
const VkClearColorValue* pColor,
|
|
uint32_t rangeCount,
|
|
const VkImageSubresourceRange* pRanges)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
RADV_FROM_HANDLE(radv_image, image, image_h);
|
|
union meta_saved_state saved_state;
|
|
bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
|
|
|
|
if (cs)
|
|
radv_meta_begin_cleari(cmd_buffer, &saved_state.compute);
|
|
else
|
|
radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state.gfx, cmd_buffer);
|
|
|
|
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
|
|
(const VkClearValue *) pColor,
|
|
rangeCount, pRanges, cs);
|
|
|
|
if (cs)
|
|
radv_meta_end_cleari(cmd_buffer, &saved_state.compute);
|
|
else
|
|
radv_meta_restore(&saved_state.gfx, cmd_buffer);
|
|
}
|
|
|
|
void radv_CmdClearDepthStencilImage(
|
|
VkCommandBuffer commandBuffer,
|
|
VkImage image_h,
|
|
VkImageLayout imageLayout,
|
|
const VkClearDepthStencilValue* pDepthStencil,
|
|
uint32_t rangeCount,
|
|
const VkImageSubresourceRange* pRanges)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
RADV_FROM_HANDLE(radv_image, image, image_h);
|
|
struct radv_meta_saved_state saved_state;
|
|
|
|
radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
|
|
|
|
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
|
|
(const VkClearValue *) pDepthStencil,
|
|
rangeCount, pRanges, false);
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|
|
|
|
void radv_CmdClearAttachments(
|
|
VkCommandBuffer commandBuffer,
|
|
uint32_t attachmentCount,
|
|
const VkClearAttachment* pAttachments,
|
|
uint32_t rectCount,
|
|
const VkClearRect* pRects)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
struct radv_meta_saved_state saved_state;
|
|
enum radv_cmd_flush_bits pre_flush = 0;
|
|
enum radv_cmd_flush_bits post_flush = 0;
|
|
|
|
if (!cmd_buffer->state.subpass)
|
|
return;
|
|
|
|
radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
|
|
|
|
/* FINISHME: We can do better than this dumb loop. It thrashes too much
|
|
* state.
|
|
*/
|
|
for (uint32_t a = 0; a < attachmentCount; ++a) {
|
|
for (uint32_t r = 0; r < rectCount; ++r) {
|
|
emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush);
|
|
}
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
cmd_buffer->state.flush_bits |= post_flush;
|
|
}
|