12d7aaf2b8
This is described in Wa_14014617373 and a programming note has been added to specification. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23682>
209 lines
8.9 KiB
C++
209 lines
8.9 KiB
C++
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file brw_fs_validate.cpp
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*
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* Implements a pass that validates various invariants of the IR. The current
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* pass only validates that GRF's uses are sane. More can be added later.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#define fsv_assert(assertion) \
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{ \
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if (!(assertion)) { \
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fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", stage_abbrev); \
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dump_instruction(inst, stderr); \
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fprintf(stderr, "%s:%d: '%s' failed\n", __FILE__, __LINE__, #assertion); \
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abort(); \
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} \
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}
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#define fsv_assert_eq(first, second) \
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{ \
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unsigned f = (first); \
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unsigned s = (second); \
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if (f != s) { \
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fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", stage_abbrev); \
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dump_instruction(inst, stderr); \
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fprintf(stderr, "%s:%d: A == B failed\n", __FILE__, __LINE__); \
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fprintf(stderr, " A = %s = %u\n", #first, f); \
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fprintf(stderr, " B = %s = %u\n", #second, s); \
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abort(); \
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} \
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}
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#define fsv_assert_ne(first, second) \
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{ \
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unsigned f = (first); \
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unsigned s = (second); \
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if (f == s) { \
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fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", stage_abbrev); \
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dump_instruction(inst, stderr); \
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fprintf(stderr, "%s:%d: A != B failed\n", __FILE__, __LINE__); \
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fprintf(stderr, " A = %s = %u\n", #first, f); \
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fprintf(stderr, " B = %s = %u\n", #second, s); \
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abort(); \
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} \
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}
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#define fsv_assert_lte(first, second) \
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{ \
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unsigned f = (first); \
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unsigned s = (second); \
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if (f > s) { \
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fprintf(stderr, "ASSERT: Scalar %s validation failed!\n", stage_abbrev); \
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dump_instruction(inst, stderr); \
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fprintf(stderr, "%s:%d: A <= B failed\n", __FILE__, __LINE__); \
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fprintf(stderr, " A = %s = %u\n", #first, f); \
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fprintf(stderr, " B = %s = %u\n", #second, s); \
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abort(); \
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} \
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}
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void
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fs_visitor::validate()
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{
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#ifndef NDEBUG
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foreach_block_and_inst (block, fs_inst, inst, cfg) {
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switch (inst->opcode) {
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case SHADER_OPCODE_URB_WRITE_LOGICAL: {
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const unsigned header_size = 1 +
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unsigned(inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE) +
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unsigned(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file != BAD_FILE);
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unsigned data_size = 0;
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for (unsigned i = header_size, j = 0; i < inst->mlen; i++, j++) {
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fsv_assert_eq(type_sz(offset(inst->src[URB_LOGICAL_SRC_DATA], bld, j).type), 4);
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data_size++;
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}
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fsv_assert_eq(header_size + data_size, inst->mlen);
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break;
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}
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case SHADER_OPCODE_SEND:
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fsv_assert(is_uniform(inst->src[0]) && is_uniform(inst->src[1]));
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break;
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case BRW_OPCODE_MOV:
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fsv_assert(inst->sources == 1);
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break;
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default:
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break;
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}
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if (inst->is_3src(compiler)) {
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const unsigned integer_sources =
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brw_reg_type_is_integer(inst->src[0].type) +
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brw_reg_type_is_integer(inst->src[1].type) +
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brw_reg_type_is_integer(inst->src[2].type);
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const unsigned float_sources =
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brw_reg_type_is_floating_point(inst->src[0].type) +
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brw_reg_type_is_floating_point(inst->src[1].type) +
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brw_reg_type_is_floating_point(inst->src[2].type);
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fsv_assert((integer_sources == 3 && float_sources == 0) ||
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(integer_sources == 0 && float_sources == 3));
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if (devinfo->ver >= 10) {
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == BRW_IMMEDIATE_VALUE)
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continue;
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switch (inst->src[i].vstride) {
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case BRW_VERTICAL_STRIDE_0:
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case BRW_VERTICAL_STRIDE_4:
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case BRW_VERTICAL_STRIDE_8:
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case BRW_VERTICAL_STRIDE_16:
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break;
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case BRW_VERTICAL_STRIDE_1:
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fsv_assert_lte(12, devinfo->ver);
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break;
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case BRW_VERTICAL_STRIDE_2:
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fsv_assert_lte(devinfo->ver, 11);
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break;
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default:
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fsv_assert(!"invalid vstride");
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break;
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}
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}
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} else if (grf_used != 0) {
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/* Only perform the pre-Gfx10 checks after register allocation has
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* occured.
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*
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* Many passes (e.g., constant copy propagation) will genenerate
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* invalid 3-source instructions with the expectation that later
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* passes (e.g., combine constants) will fix them.
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*/
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for (unsigned i = 0; i < 3; i++) {
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fsv_assert_ne(inst->src[i].file, BRW_IMMEDIATE_VALUE);
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/* A stride of 1 (the usual case) or 0, with a special
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* "repctrl" bit, is allowed. The repctrl bit doesn't work for
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* 64-bit datatypes, so if the source type is 64-bit then only
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* a stride of 1 is allowed. From the Broadwell PRM, Volume 7
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* "3D Media GPGPU", page 944:
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*
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* This is applicable to 32b datatypes and 16b datatype. 64b
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* datatypes cannot use the replicate control.
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*/
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fsv_assert_lte(inst->src[i].vstride, 1);
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if (type_sz(inst->src[i].type) > 4)
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fsv_assert_eq(inst->src[i].vstride, 1);
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}
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}
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}
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if (inst->dst.file == VGRF) {
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fsv_assert_lte(inst->dst.offset / REG_SIZE + regs_written(inst),
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alloc.sizes[inst->dst.nr]);
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}
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == VGRF) {
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fsv_assert_lte(inst->src[i].offset / REG_SIZE + regs_read(inst, i),
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alloc.sizes[inst->src[i].nr]);
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}
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}
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/* Accumulator Registers, bspec 47251:
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*
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* "When destination is accumulator with offset 0, destination
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* horizontal stride must be 1."
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*/
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if (intel_needs_workaround(devinfo, 14014617373) &&
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inst->dst.is_accumulator() &&
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inst->dst.offset == 0) {
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fsv_assert_eq(inst->dst.stride, 1);
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}
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}
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#endif
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}
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