a50d2fdb46
I've been running into failures with tests like : dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag With the load_global_const_block_intel NIR intrinsic, you can load a vec8/vec16 with a predicate. The predicate is correctly uniformized to feed into the SEND instruction's flag register. The problem is that a series of optimization first remove the find_live_channel and then changes the broadcast into a simple MOV instruction, on the assumption that the first channel is always active if there is not control flow. This is correct. But after that the cmod optimzation will remove this instruction : mov.nz.f0.0(16) null:D, vgrf16+0.0<0>:D NoMask because it seems to be equivalent to : cmp.g.f0.0(16) vgrf16:D, vgrf12:D, 63d In this case vgrf16 is the predicate to the load block SEND instruction. Since the execution mask is different between both, some of the channels of the SEND instruction end up not being loaded or loaded with the wrong predication and we end up with incorrect UBO data. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20852>
569 lines
23 KiB
C++
569 lines
23 KiB
C++
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "brw_eu.h"
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/** @file brw_fs_cmod_propagation.cpp
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*
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* Implements a pass that propagates the conditional modifier from a CMP x 0.0
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* instruction into the instruction that generated x. For instance, in this
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* sequence
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*
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* add(8) g70<1>F g69<8,8,1>F 4096F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can do the comparison as part of the ADD instruction directly:
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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*
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* If there had been a use of the flag register and another CMP using g70
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*
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* add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F
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* (+f0) sel(8) g71<F> g72<8,8,1>F g73<8,8,1>F
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* cmp.ge.f0(8) null g70<8,8,1>F 0F
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*
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* we can recognize that the CMP is generating the flag value that already
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* exists and therefore remove the instruction.
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*/
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using namespace brw;
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static bool
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cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
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fs_inst *inst)
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{
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bool read_flag = false;
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const unsigned flags_written = inst->flags_written(devinfo);
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (scan_inst->opcode == BRW_OPCODE_ADD &&
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!scan_inst->is_partial_write() &&
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scan_inst->exec_size == inst->exec_size) {
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bool negate;
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/* A CMP is basically a subtraction. The result of the
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* subtraction must be the same as the result of the addition.
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* This means that one of the operands must be negated. So (a +
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* b) vs (a == -b) or (a + -b) vs (a == b).
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*/
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if ((inst->src[0].equals(scan_inst->src[0]) &&
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inst->src[1].negative_equals(scan_inst->src[1])) ||
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(inst->src[0].equals(scan_inst->src[1]) &&
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inst->src[1].negative_equals(scan_inst->src[0]))) {
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negate = false;
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} else if ((inst->src[0].negative_equals(scan_inst->src[0]) &&
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inst->src[1].equals(scan_inst->src[1])) ||
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(inst->src[0].negative_equals(scan_inst->src[1]) &&
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inst->src[1].equals(scan_inst->src[0]))) {
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negate = true;
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} else {
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goto not_match;
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}
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/* If the scan instruction writes a different flag register than the
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* instruction we're trying to propagate from, bail.
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*
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* FINISHME: The second part of the condition may be too strong.
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* Perhaps (scan_inst->flags_written() & flags_written) !=
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* flags_written?
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*/
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if (scan_inst->flags_written(devinfo) != 0 &&
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scan_inst->flags_written(devinfo) != flags_written)
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goto not_match;
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/* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*
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* Paragraph about post_zero does not mention saturation, but
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* testing it on actual GPUs shows that conditional modifiers
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* are applied after saturation.
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*
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* * post_zero bit: This bit reflects whether the final
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* result is zero after all the clamping, normalizing,
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* or format conversion logic.
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*
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* For signed types we don't care about saturation: it won't
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* change the result of conditional modifier.
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*
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* For floating and unsigned types there two special cases,
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* when we can remove inst even if scan_inst is saturated: G
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* and LE. Since conditional modifiers are just comparisons
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* against zero, saturating positive values to the upper
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* limit never changes the result of comparison.
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*
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* For negative values:
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* (sat(x) > 0) == (x > 0) --- false
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* (sat(x) <= 0) == (x <= 0) --- true
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*/
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const enum brw_conditional_mod cond =
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negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->saturate &&
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(brw_reg_type_is_floating_point(scan_inst->dst.type) ||
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brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) &&
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(cond != BRW_CONDITIONAL_G &&
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cond != BRW_CONDITIONAL_LE))
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goto not_match;
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/* Otherwise, try propagating the conditional. */
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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scan_inst->flag_subreg = inst->flag_subreg;
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inst->remove(block, true);
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return true;
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}
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break;
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}
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not_match:
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if ((scan_inst->flags_written(devinfo) & flags_written) != 0)
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break;
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read_flag = read_flag ||
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(scan_inst->flags_read(devinfo) & flags_written) != 0;
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}
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return false;
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}
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/**
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* Propagate conditional modifiers from NOT instructions
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*
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* Attempt to convert sequences like
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*
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* or(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
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* ...
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* not.nz.f0(8) null g78<8,8,1>UD
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*
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* into
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*
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* or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
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*/
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static bool
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cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block,
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fs_inst *inst)
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{
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const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod);
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bool read_flag = false;
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const unsigned flags_written = inst->flags_written(devinfo);
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if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ)
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return false;
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (regions_overlap(scan_inst->dst, scan_inst->size_written,
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inst->src[0], inst->size_read(0))) {
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if (scan_inst->opcode != BRW_OPCODE_OR &&
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scan_inst->opcode != BRW_OPCODE_AND)
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break;
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if (scan_inst->is_partial_write() ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size)
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break;
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/* If the scan instruction writes a different flag register than the
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* instruction we're trying to propagate from, bail.
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*
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* FINISHME: The second part of the condition may be too strong.
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* Perhaps (scan_inst->flags_written() & flags_written) !=
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* flags_written?
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*/
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if (scan_inst->flags_written(devinfo) != 0 &&
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scan_inst->flags_written(devinfo) != flags_written)
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break;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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scan_inst->flag_subreg = inst->flag_subreg;
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inst->remove(block, true);
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return true;
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}
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break;
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}
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if ((scan_inst->flags_written(devinfo) & flags_written) != 0)
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break;
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read_flag = read_flag ||
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(scan_inst->flags_read(devinfo) & flags_written) != 0;
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}
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return false;
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}
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static bool
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opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
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{
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bool progress = false;
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UNUSED int ip = block->end_ip + 1;
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foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
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ip--;
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if ((inst->opcode != BRW_OPCODE_AND &&
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inst->opcode != BRW_OPCODE_CMP &&
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inst->opcode != BRW_OPCODE_MOV &&
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inst->opcode != BRW_OPCODE_NOT) ||
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inst->predicate != BRW_PREDICATE_NONE ||
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!inst->dst.is_null() ||
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(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
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inst->src[0].file != UNIFORM))
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continue;
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/* An ABS source modifier can only be handled when processing a compare
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* with a value other than zero.
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*/
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if (inst->src[0].abs &&
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(inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
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continue;
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/* Only an AND.NZ can be propagated. Many AND.Z instructions are
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* generated (for ir_unop_not in fs_visitor::emit_bool_to_cond_code).
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* Propagating those would require inverting the condition on the CMP.
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* This changes both the flag value and the register destination of the
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* CMP. That result may be used elsewhere, so we can't change its value
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* on a whim.
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*/
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if (inst->opcode == BRW_OPCODE_AND &&
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!(inst->src[1].is_one() &&
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inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate))
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continue;
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/* A CMP with a second source of zero can match with anything. A CMP
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* with a second source that is not zero can only match with an ADD
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* instruction.
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*
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* Only apply this optimization to float-point sources. It can fail for
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* integers. For inputs a = 0x80000000, b = 4, int(0x80000000) < 4, but
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* int(0x80000000) - 4 overflows and results in 0x7ffffffc. that's not
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* less than zero, so the flags get set differently than for (a < b).
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*/
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if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
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if (brw_reg_type_is_floating_point(inst->src[0].type) &&
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cmod_propagate_cmp_to_add(devinfo, block, inst))
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progress = true;
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continue;
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}
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if (inst->opcode == BRW_OPCODE_NOT) {
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progress = cmod_propagate_not(devinfo, block, inst) || progress;
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continue;
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}
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bool read_flag = false;
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const unsigned flags_written = inst->flags_written(devinfo);
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foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
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if (regions_overlap(scan_inst->dst, scan_inst->size_written,
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inst->src[0], inst->size_read(0))) {
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/* If the scan instruction writes a different flag register than
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* the instruction we're trying to propagate from, bail.
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*
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* FINISHME: The second part of the condition may be too strong.
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* Perhaps (scan_inst->flags_written() & flags_written) !=
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* flags_written?
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*/
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if (scan_inst->flags_written(devinfo) != 0 &&
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scan_inst->flags_written(devinfo) != flags_written)
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break;
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if (scan_inst->is_partial_write() ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size)
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break;
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/* If the write mask is different we can't propagate. */
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if (scan_inst->force_writemask_all != inst->force_writemask_all)
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break;
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/* CMP's result is the same regardless of dest type. */
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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scan_inst->opcode == BRW_OPCODE_CMP &&
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brw_reg_type_is_integer(inst->dst.type)) {
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inst->remove(block, true);
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progress = true;
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break;
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}
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/* If the AND wasn't handled by the previous case, it isn't safe
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* to remove it.
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*/
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if (inst->opcode == BRW_OPCODE_AND)
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break;
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if (inst->opcode == BRW_OPCODE_MOV) {
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if (brw_reg_type_is_floating_point(scan_inst->dst.type)) {
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/* If the destination type of scan_inst is floating-point,
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* then:
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*
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* - The source of the MOV instruction must be the same
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* type.
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*
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* - The destination of the MOV instruction must be float
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* point with a size at least as large as the destination
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* of inst. Size-reducing f2f conversions could cause
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* non-zero values to become zero, etc.
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*/
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if (scan_inst->dst.type != inst->src[0].type)
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break;
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if (!brw_reg_type_is_floating_point(inst->dst.type))
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break;
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if (type_sz(scan_inst->dst.type) > type_sz(inst->dst.type))
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break;
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} else {
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/* If the destination type of scan_inst is integer, then:
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*
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* - The source of the MOV instruction must be integer with
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* the same size.
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*
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* - If the conditional modifier is Z or NZ, then the
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* destination type of inst must either be floating point
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* (of any size) or integer with a size at least as large
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* as the destination of inst.
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*
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* - If the conditional modifier is neither Z nor NZ, then the
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* destination type of inst must either be floating point
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* (of any size) or integer with a size at least as large
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* as the destination of inst and the same signedness.
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*/
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if (!brw_reg_type_is_integer(inst->src[0].type) ||
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type_sz(scan_inst->dst.type) != type_sz(inst->src[0].type))
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break;
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if (brw_reg_type_is_integer(inst->dst.type)) {
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if (type_sz(inst->dst.type) < type_sz(scan_inst->dst.type))
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break;
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if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ &&
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brw_reg_type_is_unsigned_integer(inst->dst.type) !=
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brw_reg_type_is_unsigned_integer(scan_inst->dst.type))
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break;
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}
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}
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} else {
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/* Not safe to use inequality operators if the types are
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* different.
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*/
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if (scan_inst->dst.type != inst->src[0].type &&
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inst->conditional_mod != BRW_CONDITIONAL_Z &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ)
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break;
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/* Comparisons operate differently for ints and floats */
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if (scan_inst->dst.type != inst->dst.type) {
|
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/* Comparison result may be altered if the bit-size changes
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* since that affects range, denorms, etc
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*/
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if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type))
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break;
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if (brw_reg_type_is_floating_point(scan_inst->dst.type) !=
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brw_reg_type_is_floating_point(inst->dst.type))
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break;
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}
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}
|
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|
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/* Knowing following:
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* - CMP writes to flag register the result of
|
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* applying cmod to the `src0 - src1`.
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* After that it stores the same value to dst.
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* Other instructions first store their result to
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* dst, and then store cmod(dst) to the flag
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* register.
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* - inst is either CMP or MOV
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* - inst->dst is null
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* - inst->src[0] overlaps with scan_inst->dst
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* - inst->src[1] is zero
|
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* - scan_inst wrote to a flag register
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*
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* There can be three possible paths:
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*
|
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* - scan_inst is CMP:
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*
|
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* Considering that src0 is either 0x0 (false),
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* or 0xffffffff (true), and src1 is 0x0:
|
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*
|
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* - If inst's cmod is NZ, we can always remove
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* scan_inst: NZ is invariant for false and true. This
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* holds even if src0 is NaN: .nz is the only cmod,
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* that returns true for NaN.
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*
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* - .g is invariant if src0 has a UD type
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*
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* - .l is invariant if src0 has a D type
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*
|
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* - scan_inst and inst have the same cmod:
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*
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* If scan_inst is anything than CMP, it already
|
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* wrote the appropriate value to the flag register.
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*
|
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* - else:
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*
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* We can change cmod of scan_inst to that of inst,
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* and remove inst. It is valid as long as we make
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* sure that no instruction uses the flag register
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* between scan_inst and inst.
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*/
|
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if (!inst->src[0].negate &&
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scan_inst->flags_written(devinfo)) {
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if (scan_inst->opcode == BRW_OPCODE_CMP) {
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if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) ||
|
|
(inst->conditional_mod == BRW_CONDITIONAL_G &&
|
|
inst->src[0].type == BRW_REGISTER_TYPE_UD) ||
|
|
(inst->conditional_mod == BRW_CONDITIONAL_L &&
|
|
inst->src[0].type == BRW_REGISTER_TYPE_D)) {
|
|
inst->remove(block, true);
|
|
progress = true;
|
|
break;
|
|
}
|
|
} else if (scan_inst->conditional_mod == inst->conditional_mod) {
|
|
/* On Gfx4 and Gfx5 sel.cond will dirty the flags, but the
|
|
* flags value is not based on the result stored in the
|
|
* destination. On all other platforms sel.cond will not
|
|
* write the flags, so execution will not get to this point.
|
|
*/
|
|
if (scan_inst->opcode == BRW_OPCODE_SEL) {
|
|
assert(devinfo->ver <= 5);
|
|
} else {
|
|
inst->remove(block, true);
|
|
progress = true;
|
|
}
|
|
|
|
break;
|
|
} else if (!read_flag && scan_inst->can_do_cmod()) {
|
|
scan_inst->conditional_mod = inst->conditional_mod;
|
|
scan_inst->flag_subreg = inst->flag_subreg;
|
|
inst->remove(block, true);
|
|
progress = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* The conditional mod of the CMP/CMPN instructions behaves
|
|
* specially because the flag output is not calculated from the
|
|
* result of the instruction, but the other way around, which
|
|
* means that even if the condmod to propagate and the condmod
|
|
* from the CMP instruction are the same they will in general give
|
|
* different results because they are evaluated based on different
|
|
* inputs.
|
|
*/
|
|
if (scan_inst->opcode == BRW_OPCODE_CMP ||
|
|
scan_inst->opcode == BRW_OPCODE_CMPN)
|
|
break;
|
|
|
|
/* From the Sky Lake PRM, Vol 2a, "Multiply":
|
|
*
|
|
* "When multiplying integer data types, if one of the sources
|
|
* is a DW, the resulting full precision data is stored in
|
|
* the accumulator. However, if the destination data type is
|
|
* either W or DW, the low bits of the result are written to
|
|
* the destination register and the remaining high bits are
|
|
* discarded. This results in undefined Overflow and Sign
|
|
* flags. Therefore, conditional modifiers and saturation
|
|
* (.sat) cannot be used in this case."
|
|
*
|
|
* We just disallow cmod propagation on all integer multiplies.
|
|
*/
|
|
if (!brw_reg_type_is_floating_point(scan_inst->dst.type) &&
|
|
scan_inst->opcode == BRW_OPCODE_MUL)
|
|
break;
|
|
|
|
enum brw_conditional_mod cond =
|
|
inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
|
|
: inst->conditional_mod;
|
|
|
|
/* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":
|
|
*
|
|
* * Note that the [post condition signal] bits generated at
|
|
* the output of a compute are before the .sat.
|
|
*
|
|
* Paragraph about post_zero does not mention saturation, but
|
|
* testing it on actual GPUs shows that conditional modifiers are
|
|
* applied after saturation.
|
|
*
|
|
* * post_zero bit: This bit reflects whether the final
|
|
* result is zero after all the clamping, normalizing,
|
|
* or format conversion logic.
|
|
*
|
|
* For this reason, no additional restrictions are necessary on
|
|
* instructions with saturate.
|
|
*/
|
|
|
|
/* Otherwise, try propagating the conditional. */
|
|
if (scan_inst->can_do_cmod() &&
|
|
((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
|
|
scan_inst->conditional_mod == cond)) {
|
|
scan_inst->conditional_mod = cond;
|
|
scan_inst->flag_subreg = inst->flag_subreg;
|
|
inst->remove(block, true);
|
|
progress = true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if ((scan_inst->flags_written(devinfo) & flags_written) != 0)
|
|
break;
|
|
|
|
read_flag = read_flag ||
|
|
(scan_inst->flags_read(devinfo) & flags_written) != 0;
|
|
}
|
|
}
|
|
|
|
/* There is progress if and only if instructions were removed. */
|
|
assert(progress == (block->end_ip_delta != 0));
|
|
|
|
return progress;
|
|
}
|
|
|
|
bool
|
|
fs_visitor::opt_cmod_propagation()
|
|
{
|
|
bool progress = false;
|
|
|
|
foreach_block_reverse(block, cfg) {
|
|
progress = opt_cmod_propagation_local(devinfo, block) || progress;
|
|
}
|
|
|
|
if (progress) {
|
|
cfg->adjust_block_ips();
|
|
|
|
invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
|
|
}
|
|
|
|
return progress;
|
|
}
|