1227 lines
43 KiB
C
1227 lines
43 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "util/mesa-sha1.h"
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#include "common/gen_l3_config.h"
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#include "anv_private.h"
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#include "brw_nir.h"
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#include "anv_nir.h"
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#include "spirv/nir_spirv.h"
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/* Needed for SWIZZLE macros */
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#include "program/prog_instruction.h"
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// Shader functions
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VkResult anv_CreateShaderModule(
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VkDevice _device,
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const VkShaderModuleCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkShaderModule* pShaderModule)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_shader_module *module;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
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assert(pCreateInfo->flags == 0);
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module = anv_alloc2(&device->alloc, pAllocator,
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sizeof(*module) + pCreateInfo->codeSize, 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (module == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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module->size = pCreateInfo->codeSize;
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memcpy(module->data, pCreateInfo->pCode, module->size);
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_mesa_sha1_compute(module->data, module->size, module->sha1);
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*pShaderModule = anv_shader_module_to_handle(module);
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return VK_SUCCESS;
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}
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void anv_DestroyShaderModule(
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VkDevice _device,
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VkShaderModule _module,
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const VkAllocationCallbacks* pAllocator)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_shader_module, module, _module);
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anv_free2(&device->alloc, pAllocator, module);
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}
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#define SPIR_V_MAGIC_NUMBER 0x07230203
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/* Eventually, this will become part of anv_CreateShader. Unfortunately,
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* we can't do that yet because we don't have the ability to copy nir.
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*/
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static nir_shader *
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anv_shader_compile_to_nir(struct anv_device *device,
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struct anv_shader_module *module,
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const char *entrypoint_name,
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gl_shader_stage stage,
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const VkSpecializationInfo *spec_info)
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{
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if (strcmp(entrypoint_name, "main") != 0) {
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anv_finishme("Multiple shaders per module not really supported");
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}
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const struct brw_compiler *compiler =
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device->instance->physicalDevice.compiler;
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const nir_shader_compiler_options *nir_options =
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compiler->glsl_compiler_options[stage].NirOptions;
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uint32_t *spirv = (uint32_t *) module->data;
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assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
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assert(module->size % 4 == 0);
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uint32_t num_spec_entries = 0;
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struct nir_spirv_specialization *spec_entries = NULL;
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if (spec_info && spec_info->mapEntryCount > 0) {
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num_spec_entries = spec_info->mapEntryCount;
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spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
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for (uint32_t i = 0; i < num_spec_entries; i++) {
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VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
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const void *data = spec_info->pData + entry.offset;
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assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
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spec_entries[i].id = spec_info->pMapEntries[i].constantID;
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spec_entries[i].data = *(const uint32_t *)data;
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}
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}
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nir_function *entry_point =
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spirv_to_nir(spirv, module->size / 4,
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spec_entries, num_spec_entries,
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stage, entrypoint_name, nir_options);
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nir_shader *nir = entry_point->shader;
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assert(nir->stage == stage);
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nir_validate_shader(nir);
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free(spec_entries);
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if (stage == MESA_SHADER_FRAGMENT) {
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nir_lower_wpos_center(nir);
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nir_validate_shader(nir);
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}
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nir_lower_returns(nir);
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nir_validate_shader(nir);
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nir_inline_functions(nir);
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nir_validate_shader(nir);
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/* Pick off the single entrypoint that we want */
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foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
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if (func != entry_point)
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exec_node_remove(&func->node);
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}
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assert(exec_list_length(&nir->functions) == 1);
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entry_point->name = ralloc_strdup(entry_point, "main");
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nir_remove_dead_variables(nir, nir_var_shader_in);
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nir_remove_dead_variables(nir, nir_var_shader_out);
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nir_remove_dead_variables(nir, nir_var_system_value);
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nir_validate_shader(nir);
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nir_propagate_invariant(nir);
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nir_validate_shader(nir);
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nir_lower_io_to_temporaries(entry_point->shader, entry_point->impl,
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true, false);
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nir_lower_system_values(nir);
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nir_validate_shader(nir);
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/* Vulkan uses the separate-shader linking model */
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nir->info.separate_shader = true;
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nir = brw_preprocess_nir(compiler, nir);
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nir_shader_gather_info(nir, entry_point->impl);
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nir_variable_mode indirect_mask = 0;
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if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
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indirect_mask |= nir_var_shader_in;
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if (compiler->glsl_compiler_options[stage].EmitNoIndirectOutput)
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indirect_mask |= nir_var_shader_out;
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if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
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indirect_mask |= nir_var_local;
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nir_lower_indirect_derefs(nir, indirect_mask);
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return nir;
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}
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void anv_DestroyPipeline(
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VkDevice _device,
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VkPipeline _pipeline,
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const VkAllocationCallbacks* pAllocator)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
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anv_reloc_list_finish(&pipeline->batch_relocs,
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pAllocator ? pAllocator : &device->alloc);
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if (pipeline->blend_state.map)
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anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
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for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
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if (pipeline->shaders[s])
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anv_shader_bin_unref(device, pipeline->shaders[s]);
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}
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anv_free2(&device->alloc, pAllocator, pipeline);
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}
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static const uint32_t vk_to_gen_primitive_type[] = {
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[VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
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[VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
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[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
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[VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
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/* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
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};
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static void
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populate_sampler_prog_key(const struct gen_device_info *devinfo,
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struct brw_sampler_prog_key_data *key)
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{
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/* XXX: Handle texture swizzle on HSW- */
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for (int i = 0; i < MAX_SAMPLERS; i++) {
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/* Assume color sampler, no swizzling. (Works for BDW+) */
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key->swizzles[i] = SWIZZLE_XYZW;
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}
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}
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static void
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populate_vs_prog_key(const struct gen_device_info *devinfo,
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struct brw_vs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_sampler_prog_key(devinfo, &key->tex);
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/* XXX: Handle vertex input work-arounds */
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/* XXX: Handle sampler_prog_key */
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}
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static void
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populate_gs_prog_key(const struct gen_device_info *devinfo,
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struct brw_gs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_sampler_prog_key(devinfo, &key->tex);
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}
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static void
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populate_wm_prog_key(const struct gen_device_info *devinfo,
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const VkGraphicsPipelineCreateInfo *info,
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struct brw_wm_prog_key *key)
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{
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ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
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memset(key, 0, sizeof(*key));
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populate_sampler_prog_key(devinfo, &key->tex);
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/* TODO: Fill out key->input_slots_valid */
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/* Vulkan doesn't specify a default */
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key->high_quality_derivatives = false;
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/* XXX Vulkan doesn't appear to specify */
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key->clamp_fragment_color = false;
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key->nr_color_regions =
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render_pass->subpasses[info->subpass].color_count;
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key->replicate_alpha = key->nr_color_regions > 1 &&
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info->pMultisampleState &&
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info->pMultisampleState->alphaToCoverageEnable;
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if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
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/* We should probably pull this out of the shader, but it's fairly
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* harmless to compute it and then let dead-code take care of it.
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*/
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key->persample_interp =
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(info->pMultisampleState->minSampleShading *
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info->pMultisampleState->rasterizationSamples) > 1;
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key->multisample_fbo = true;
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}
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}
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static void
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populate_cs_prog_key(const struct gen_device_info *devinfo,
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struct brw_cs_prog_key *key)
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{
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memset(key, 0, sizeof(*key));
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populate_sampler_prog_key(devinfo, &key->tex);
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}
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static nir_shader *
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anv_pipeline_compile(struct anv_pipeline *pipeline,
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struct anv_shader_module *module,
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const char *entrypoint,
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gl_shader_stage stage,
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const VkSpecializationInfo *spec_info,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map)
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{
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nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
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module, entrypoint, stage,
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spec_info);
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if (nir == NULL)
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return NULL;
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anv_nir_lower_push_constants(nir);
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/* Figure out the number of parameters */
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prog_data->nr_params = 0;
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if (nir->num_uniforms > 0) {
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/* If the shader uses any push constants at all, we'll just give
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* them the maximum possible number
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*/
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assert(nir->num_uniforms <= MAX_PUSH_CONSTANTS_SIZE);
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prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
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}
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if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
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prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
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if (nir->info.num_images > 0) {
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prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
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pipeline->needs_data_cache = true;
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}
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if (stage == MESA_SHADER_COMPUTE)
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((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
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prog_data->nr_params++; /* The CS Thread ID uniform */
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if (nir->info.num_ssbos > 0)
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pipeline->needs_data_cache = true;
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if (prog_data->nr_params > 0) {
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/* XXX: I think we're leaking this */
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prog_data->param = (const union gl_constant_value **)
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malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
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/* We now set the param values to be offsets into a
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* anv_push_constant_data structure. Since the compiler doesn't
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* actually dereference any of the gl_constant_value pointers in the
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* params array, it doesn't really matter what we put here.
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*/
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struct anv_push_constants *null_data = NULL;
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if (nir->num_uniforms > 0) {
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/* Fill out the push constants section of the param array */
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for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
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prog_data->param[i] = (const union gl_constant_value *)
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&null_data->client_data[i * sizeof(float)];
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}
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}
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/* Set up dynamic offsets */
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anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
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/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
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if (pipeline->layout)
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anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
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/* nir_lower_io will only handle the push constants; we need to set this
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* to the full number of possible uniforms.
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*/
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nir->num_uniforms = prog_data->nr_params * 4;
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return nir;
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}
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static void
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anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
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{
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prog_data->binding_table.size_bytes = 0;
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prog_data->binding_table.texture_start = bias;
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prog_data->binding_table.gather_texture_start = bias;
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prog_data->binding_table.ubo_start = bias;
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prog_data->binding_table.ssbo_start = bias;
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prog_data->binding_table.image_start = bias;
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}
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static struct anv_shader_bin *
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anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
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struct anv_pipeline_cache *cache,
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const void *key_data, uint32_t key_size,
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const void *kernel_data, uint32_t kernel_size,
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const void *prog_data, uint32_t prog_data_size,
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const struct anv_pipeline_bind_map *bind_map)
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{
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if (cache) {
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return anv_pipeline_cache_upload_kernel(cache, key_data, key_size,
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kernel_data, kernel_size,
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prog_data, prog_data_size,
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bind_map);
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} else {
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return anv_shader_bin_create(pipeline->device, key_data, key_size,
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kernel_data, kernel_size,
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prog_data, prog_data_size, bind_map);
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}
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}
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static void
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anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
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gl_shader_stage stage,
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struct anv_shader_bin *shader)
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{
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pipeline->shaders[stage] = shader;
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pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
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}
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static VkResult
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anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
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struct anv_pipeline_cache *cache,
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const VkGraphicsPipelineCreateInfo *info,
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struct anv_shader_module *module,
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const char *entrypoint,
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const VkSpecializationInfo *spec_info)
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{
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const struct brw_compiler *compiler =
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pipeline->device->instance->physicalDevice.compiler;
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struct anv_pipeline_bind_map map;
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struct brw_vs_prog_key key;
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struct anv_shader_bin *bin = NULL;
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unsigned char sha1[20];
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populate_vs_prog_key(&pipeline->device->info, &key);
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if (cache) {
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anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
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pipeline->layout, spec_info);
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bin = anv_pipeline_cache_search(cache, sha1, 20);
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}
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if (bin == NULL) {
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struct brw_vs_prog_data prog_data = { 0, };
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struct anv_pipeline_binding surface_to_descriptor[256];
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struct anv_pipeline_binding sampler_to_descriptor[256];
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map = (struct anv_pipeline_bind_map) {
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.surface_to_descriptor = surface_to_descriptor,
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.sampler_to_descriptor = sampler_to_descriptor
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};
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nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
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MESA_SHADER_VERTEX, spec_info,
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&prog_data.base.base, &map);
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if (nir == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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anv_fill_binding_table(&prog_data.base.base, 0);
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void *mem_ctx = ralloc_context(NULL);
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ralloc_steal(mem_ctx, nir);
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|
|
prog_data.inputs_read = nir->info.inputs_read;
|
|
|
|
brw_compute_vue_map(&pipeline->device->info,
|
|
&prog_data.base.vue_map,
|
|
nir->info.outputs_written,
|
|
nir->info.separate_shader);
|
|
|
|
unsigned code_size;
|
|
const unsigned *shader_code =
|
|
brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
|
|
NULL, false, -1, &code_size, NULL);
|
|
if (shader_code == NULL) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
|
|
shader_code, code_size,
|
|
&prog_data, sizeof(prog_data), &map);
|
|
if (!bin) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
ralloc_free(mem_ctx);
|
|
}
|
|
|
|
const struct brw_vs_prog_data *vs_prog_data =
|
|
(const struct brw_vs_prog_data *)anv_shader_bin_get_prog_data(bin);
|
|
|
|
if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
|
|
pipeline->vs_simd8 = bin->kernel.offset;
|
|
pipeline->vs_vec4 = NO_KERNEL;
|
|
} else {
|
|
pipeline->vs_simd8 = NO_KERNEL;
|
|
pipeline->vs_vec4 = bin->kernel.offset;
|
|
}
|
|
|
|
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
static VkResult
|
|
anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
|
|
struct anv_pipeline_cache *cache,
|
|
const VkGraphicsPipelineCreateInfo *info,
|
|
struct anv_shader_module *module,
|
|
const char *entrypoint,
|
|
const VkSpecializationInfo *spec_info)
|
|
{
|
|
const struct brw_compiler *compiler =
|
|
pipeline->device->instance->physicalDevice.compiler;
|
|
struct anv_pipeline_bind_map map;
|
|
struct brw_gs_prog_key key;
|
|
struct anv_shader_bin *bin = NULL;
|
|
unsigned char sha1[20];
|
|
|
|
populate_gs_prog_key(&pipeline->device->info, &key);
|
|
|
|
if (cache) {
|
|
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
|
|
pipeline->layout, spec_info);
|
|
bin = anv_pipeline_cache_search(cache, sha1, 20);
|
|
}
|
|
|
|
if (bin == NULL) {
|
|
struct brw_gs_prog_data prog_data = { 0, };
|
|
struct anv_pipeline_binding surface_to_descriptor[256];
|
|
struct anv_pipeline_binding sampler_to_descriptor[256];
|
|
|
|
map = (struct anv_pipeline_bind_map) {
|
|
.surface_to_descriptor = surface_to_descriptor,
|
|
.sampler_to_descriptor = sampler_to_descriptor
|
|
};
|
|
|
|
nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
|
|
MESA_SHADER_GEOMETRY, spec_info,
|
|
&prog_data.base.base, &map);
|
|
if (nir == NULL)
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
anv_fill_binding_table(&prog_data.base.base, 0);
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
ralloc_steal(mem_ctx, nir);
|
|
|
|
brw_compute_vue_map(&pipeline->device->info,
|
|
&prog_data.base.vue_map,
|
|
nir->info.outputs_written,
|
|
nir->info.separate_shader);
|
|
|
|
unsigned code_size;
|
|
const unsigned *shader_code =
|
|
brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
|
|
NULL, -1, &code_size, NULL);
|
|
if (shader_code == NULL) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
/* TODO: SIMD8 GS */
|
|
bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
|
|
shader_code, code_size,
|
|
&prog_data, sizeof(prog_data), &map);
|
|
if (!bin) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
ralloc_free(mem_ctx);
|
|
}
|
|
|
|
pipeline->gs_kernel = bin->kernel.offset;
|
|
|
|
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
static VkResult
|
|
anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
|
|
struct anv_pipeline_cache *cache,
|
|
const VkGraphicsPipelineCreateInfo *info,
|
|
struct anv_shader_module *module,
|
|
const char *entrypoint,
|
|
const VkSpecializationInfo *spec_info)
|
|
{
|
|
const struct brw_compiler *compiler =
|
|
pipeline->device->instance->physicalDevice.compiler;
|
|
struct anv_pipeline_bind_map map;
|
|
struct brw_wm_prog_key key;
|
|
struct anv_shader_bin *bin = NULL;
|
|
unsigned char sha1[20];
|
|
|
|
populate_wm_prog_key(&pipeline->device->info, info, &key);
|
|
|
|
if (cache) {
|
|
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
|
|
pipeline->layout, spec_info);
|
|
bin = anv_pipeline_cache_search(cache, sha1, 20);
|
|
}
|
|
|
|
if (bin == NULL) {
|
|
struct brw_wm_prog_data prog_data = { 0, };
|
|
struct anv_pipeline_binding surface_to_descriptor[256];
|
|
struct anv_pipeline_binding sampler_to_descriptor[256];
|
|
|
|
map = (struct anv_pipeline_bind_map) {
|
|
.surface_to_descriptor = surface_to_descriptor + 8,
|
|
.sampler_to_descriptor = sampler_to_descriptor
|
|
};
|
|
|
|
nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
|
|
MESA_SHADER_FRAGMENT, spec_info,
|
|
&prog_data.base, &map);
|
|
if (nir == NULL)
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
unsigned num_rts = 0;
|
|
struct anv_pipeline_binding rt_bindings[8];
|
|
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
|
|
nir_foreach_variable_safe(var, &nir->outputs) {
|
|
if (var->data.location < FRAG_RESULT_DATA0)
|
|
continue;
|
|
|
|
unsigned rt = var->data.location - FRAG_RESULT_DATA0;
|
|
if (rt >= key.nr_color_regions) {
|
|
/* Out-of-bounds, throw it away */
|
|
var->data.mode = nir_var_local;
|
|
exec_node_remove(&var->node);
|
|
exec_list_push_tail(&impl->locals, &var->node);
|
|
continue;
|
|
}
|
|
|
|
/* Give it a new, compacted, location */
|
|
var->data.location = FRAG_RESULT_DATA0 + num_rts;
|
|
|
|
unsigned array_len =
|
|
glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
|
|
assert(num_rts + array_len <= 8);
|
|
|
|
for (unsigned i = 0; i < array_len; i++) {
|
|
rt_bindings[num_rts + i] = (struct anv_pipeline_binding) {
|
|
.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
|
|
.binding = 0,
|
|
.index = rt + i,
|
|
};
|
|
}
|
|
|
|
num_rts += array_len;
|
|
}
|
|
|
|
if (num_rts == 0) {
|
|
/* If we have no render targets, we need a null render target */
|
|
rt_bindings[0] = (struct anv_pipeline_binding) {
|
|
.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
|
|
.binding = 0,
|
|
.index = UINT8_MAX,
|
|
};
|
|
num_rts = 1;
|
|
}
|
|
|
|
assert(num_rts <= 8);
|
|
map.surface_to_descriptor -= num_rts;
|
|
map.surface_count += num_rts;
|
|
assert(map.surface_count <= 256);
|
|
memcpy(map.surface_to_descriptor, rt_bindings,
|
|
num_rts * sizeof(*rt_bindings));
|
|
|
|
anv_fill_binding_table(&prog_data.base, num_rts);
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
ralloc_steal(mem_ctx, nir);
|
|
|
|
unsigned code_size;
|
|
const unsigned *shader_code =
|
|
brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
|
|
NULL, -1, -1, true, false, &code_size, NULL);
|
|
if (shader_code == NULL) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
|
|
shader_code, code_size,
|
|
&prog_data, sizeof(prog_data), &map);
|
|
if (!bin) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
ralloc_free(mem_ctx);
|
|
}
|
|
|
|
pipeline->ps_ksp0 = bin->kernel.offset;
|
|
|
|
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
VkResult
|
|
anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
|
|
struct anv_pipeline_cache *cache,
|
|
const VkComputePipelineCreateInfo *info,
|
|
struct anv_shader_module *module,
|
|
const char *entrypoint,
|
|
const VkSpecializationInfo *spec_info)
|
|
{
|
|
const struct brw_compiler *compiler =
|
|
pipeline->device->instance->physicalDevice.compiler;
|
|
struct anv_pipeline_bind_map map;
|
|
struct brw_cs_prog_key key;
|
|
struct anv_shader_bin *bin = NULL;
|
|
unsigned char sha1[20];
|
|
|
|
populate_cs_prog_key(&pipeline->device->info, &key);
|
|
|
|
if (cache) {
|
|
anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
|
|
pipeline->layout, spec_info);
|
|
bin = anv_pipeline_cache_search(cache, sha1, 20);
|
|
}
|
|
|
|
if (bin == NULL) {
|
|
struct brw_cs_prog_data prog_data = { 0, };
|
|
struct anv_pipeline_binding surface_to_descriptor[256];
|
|
struct anv_pipeline_binding sampler_to_descriptor[256];
|
|
|
|
map = (struct anv_pipeline_bind_map) {
|
|
.surface_to_descriptor = surface_to_descriptor,
|
|
.sampler_to_descriptor = sampler_to_descriptor
|
|
};
|
|
|
|
nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
|
|
MESA_SHADER_COMPUTE, spec_info,
|
|
&prog_data.base, &map);
|
|
if (nir == NULL)
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
anv_fill_binding_table(&prog_data.base, 1);
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
ralloc_steal(mem_ctx, nir);
|
|
|
|
unsigned code_size;
|
|
const unsigned *shader_code =
|
|
brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
|
|
-1, &code_size, NULL);
|
|
if (shader_code == NULL) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
bin = anv_pipeline_upload_kernel(pipeline, cache, sha1, 20,
|
|
shader_code, code_size,
|
|
&prog_data, sizeof(prog_data), &map);
|
|
if (!bin) {
|
|
ralloc_free(mem_ctx);
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
}
|
|
|
|
ralloc_free(mem_ctx);
|
|
}
|
|
|
|
pipeline->cs_simd = bin->kernel.offset;
|
|
|
|
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* Copy pipeline state not marked as dynamic.
|
|
* Dynamic state is pipeline state which hasn't been provided at pipeline
|
|
* creation time, but is dynamically provided afterwards using various
|
|
* vkCmdSet* functions.
|
|
*
|
|
* The set of state considered "non_dynamic" is determined by the pieces of
|
|
* state that have their corresponding VkDynamicState enums omitted from
|
|
* VkPipelineDynamicStateCreateInfo::pDynamicStates.
|
|
*
|
|
* @param[out] pipeline Destination non_dynamic state.
|
|
* @param[in] pCreateInfo Source of non_dynamic state to be copied.
|
|
*/
|
|
static void
|
|
copy_non_dynamic_state(struct anv_pipeline *pipeline,
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo)
|
|
{
|
|
anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
|
|
ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
|
|
struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
|
|
|
|
pipeline->dynamic_state = default_dynamic_state;
|
|
|
|
if (pCreateInfo->pDynamicState) {
|
|
/* Remove all of the states that are marked as dynamic */
|
|
uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
|
|
for (uint32_t s = 0; s < count; s++)
|
|
states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
|
|
}
|
|
|
|
struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
|
|
|
|
/* Section 9.2 of the Vulkan 1.0.15 spec says:
|
|
*
|
|
* pViewportState is [...] NULL if the pipeline
|
|
* has rasterization disabled.
|
|
*/
|
|
if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
|
|
assert(pCreateInfo->pViewportState);
|
|
|
|
dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
|
|
if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
|
|
typed_memcpy(dynamic->viewport.viewports,
|
|
pCreateInfo->pViewportState->pViewports,
|
|
pCreateInfo->pViewportState->viewportCount);
|
|
}
|
|
|
|
dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
|
|
if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
|
|
typed_memcpy(dynamic->scissor.scissors,
|
|
pCreateInfo->pViewportState->pScissors,
|
|
pCreateInfo->pViewportState->scissorCount);
|
|
}
|
|
}
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
|
|
assert(pCreateInfo->pRasterizationState);
|
|
dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
|
|
}
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
|
|
assert(pCreateInfo->pRasterizationState);
|
|
dynamic->depth_bias.bias =
|
|
pCreateInfo->pRasterizationState->depthBiasConstantFactor;
|
|
dynamic->depth_bias.clamp =
|
|
pCreateInfo->pRasterizationState->depthBiasClamp;
|
|
dynamic->depth_bias.slope =
|
|
pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
|
|
}
|
|
|
|
/* Section 9.2 of the Vulkan 1.0.15 spec says:
|
|
*
|
|
* pColorBlendState is [...] NULL if the pipeline has rasterization
|
|
* disabled or if the subpass of the render pass the pipeline is
|
|
* created against does not use any color attachments.
|
|
*/
|
|
bool uses_color_att = false;
|
|
for (unsigned i = 0; i < subpass->color_count; ++i) {
|
|
if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
|
|
uses_color_att = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (uses_color_att &&
|
|
!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
|
|
assert(pCreateInfo->pColorBlendState);
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
|
|
typed_memcpy(dynamic->blend_constants,
|
|
pCreateInfo->pColorBlendState->blendConstants, 4);
|
|
}
|
|
|
|
/* If there is no depthstencil attachment, then don't read
|
|
* pDepthStencilState. The Vulkan spec states that pDepthStencilState may
|
|
* be NULL in this case. Even if pDepthStencilState is non-NULL, there is
|
|
* no need to override the depthstencil defaults in
|
|
* anv_pipeline::dynamic_state when there is no depthstencil attachment.
|
|
*
|
|
* Section 9.2 of the Vulkan 1.0.15 spec says:
|
|
*
|
|
* pDepthStencilState is [...] NULL if the pipeline has rasterization
|
|
* disabled or if the subpass of the render pass the pipeline is created
|
|
* against does not use a depth/stencil attachment.
|
|
*/
|
|
if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
|
|
subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
|
|
assert(pCreateInfo->pDepthStencilState);
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
|
|
dynamic->depth_bounds.min =
|
|
pCreateInfo->pDepthStencilState->minDepthBounds;
|
|
dynamic->depth_bounds.max =
|
|
pCreateInfo->pDepthStencilState->maxDepthBounds;
|
|
}
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
|
|
dynamic->stencil_compare_mask.front =
|
|
pCreateInfo->pDepthStencilState->front.compareMask;
|
|
dynamic->stencil_compare_mask.back =
|
|
pCreateInfo->pDepthStencilState->back.compareMask;
|
|
}
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
|
|
dynamic->stencil_write_mask.front =
|
|
pCreateInfo->pDepthStencilState->front.writeMask;
|
|
dynamic->stencil_write_mask.back =
|
|
pCreateInfo->pDepthStencilState->back.writeMask;
|
|
}
|
|
|
|
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
|
|
dynamic->stencil_reference.front =
|
|
pCreateInfo->pDepthStencilState->front.reference;
|
|
dynamic->stencil_reference.back =
|
|
pCreateInfo->pDepthStencilState->back.reference;
|
|
}
|
|
}
|
|
|
|
pipeline->dynamic_state_mask = states;
|
|
}
|
|
|
|
static void
|
|
anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
|
|
{
|
|
struct anv_render_pass *renderpass = NULL;
|
|
struct anv_subpass *subpass = NULL;
|
|
|
|
/* Assert that all required members of VkGraphicsPipelineCreateInfo are
|
|
* present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
|
|
*/
|
|
assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
|
|
|
|
renderpass = anv_render_pass_from_handle(info->renderPass);
|
|
assert(renderpass);
|
|
|
|
assert(info->subpass < renderpass->subpass_count);
|
|
subpass = &renderpass->subpasses[info->subpass];
|
|
|
|
assert(info->stageCount >= 1);
|
|
assert(info->pVertexInputState);
|
|
assert(info->pInputAssemblyState);
|
|
assert(info->pRasterizationState);
|
|
if (!info->pRasterizationState->rasterizerDiscardEnable) {
|
|
assert(info->pViewportState);
|
|
assert(info->pMultisampleState);
|
|
|
|
if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
|
|
assert(info->pDepthStencilState);
|
|
|
|
if (subpass && subpass->color_count > 0)
|
|
assert(info->pColorBlendState);
|
|
}
|
|
|
|
for (uint32_t i = 0; i < info->stageCount; ++i) {
|
|
switch (info->pStages[i].stage) {
|
|
case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
|
|
case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
|
|
assert(info->pTessellationState);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Calculate the desired L3 partitioning based on the current state of the
|
|
* pipeline. For now this simply returns the conservative defaults calculated
|
|
* by get_default_l3_weights(), but we could probably do better by gathering
|
|
* more statistics from the pipeline state (e.g. guess of expected URB usage
|
|
* and bound surfaces), or by using feed-back from performance counters.
|
|
*/
|
|
void
|
|
anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
|
|
{
|
|
const struct gen_device_info *devinfo = &pipeline->device->info;
|
|
|
|
const struct gen_l3_weights w =
|
|
gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
|
|
|
|
pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
|
|
pipeline->urb.total_size =
|
|
gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
|
|
}
|
|
|
|
VkResult
|
|
anv_pipeline_init(struct anv_pipeline *pipeline,
|
|
struct anv_device *device,
|
|
struct anv_pipeline_cache *cache,
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
|
const VkAllocationCallbacks *alloc)
|
|
{
|
|
VkResult result;
|
|
|
|
anv_validate {
|
|
anv_pipeline_validate_create_info(pCreateInfo);
|
|
}
|
|
|
|
if (alloc == NULL)
|
|
alloc = &device->alloc;
|
|
|
|
pipeline->device = device;
|
|
pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
|
|
|
|
result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
|
|
if (result != VK_SUCCESS)
|
|
return result;
|
|
|
|
pipeline->batch.alloc = alloc;
|
|
pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
|
|
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
|
|
pipeline->batch.relocs = &pipeline->batch_relocs;
|
|
|
|
copy_non_dynamic_state(pipeline, pCreateInfo);
|
|
pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
|
|
pCreateInfo->pRasterizationState->depthClampEnable;
|
|
|
|
pipeline->needs_data_cache = false;
|
|
|
|
/* When we free the pipeline, we detect stages based on the NULL status
|
|
* of various prog_data pointers. Make them NULL by default.
|
|
*/
|
|
memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
|
|
|
|
pipeline->vs_simd8 = NO_KERNEL;
|
|
pipeline->vs_vec4 = NO_KERNEL;
|
|
pipeline->gs_kernel = NO_KERNEL;
|
|
pipeline->ps_ksp0 = NO_KERNEL;
|
|
|
|
pipeline->active_stages = 0;
|
|
|
|
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
|
|
struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
|
|
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
|
|
gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
|
|
pStages[stage] = &pCreateInfo->pStages[i];
|
|
modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
|
|
}
|
|
|
|
if (modules[MESA_SHADER_VERTEX]) {
|
|
result = anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
|
|
modules[MESA_SHADER_VERTEX],
|
|
pStages[MESA_SHADER_VERTEX]->pName,
|
|
pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
|
|
if (result != VK_SUCCESS)
|
|
goto compile_fail;
|
|
}
|
|
|
|
if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
|
|
anv_finishme("no tessellation support");
|
|
|
|
if (modules[MESA_SHADER_GEOMETRY]) {
|
|
result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
|
|
modules[MESA_SHADER_GEOMETRY],
|
|
pStages[MESA_SHADER_GEOMETRY]->pName,
|
|
pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
|
|
if (result != VK_SUCCESS)
|
|
goto compile_fail;
|
|
}
|
|
|
|
if (modules[MESA_SHADER_FRAGMENT]) {
|
|
result = anv_pipeline_compile_fs(pipeline, cache, pCreateInfo,
|
|
modules[MESA_SHADER_FRAGMENT],
|
|
pStages[MESA_SHADER_FRAGMENT]->pName,
|
|
pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
|
|
if (result != VK_SUCCESS)
|
|
goto compile_fail;
|
|
}
|
|
|
|
assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
|
|
|
|
anv_pipeline_setup_l3_config(pipeline, false);
|
|
|
|
const VkPipelineVertexInputStateCreateInfo *vi_info =
|
|
pCreateInfo->pVertexInputState;
|
|
|
|
const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
|
|
|
|
pipeline->vb_used = 0;
|
|
for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
|
|
const VkVertexInputAttributeDescription *desc =
|
|
&vi_info->pVertexAttributeDescriptions[i];
|
|
|
|
if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
|
|
pipeline->vb_used |= 1 << desc->binding;
|
|
}
|
|
|
|
for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
|
|
const VkVertexInputBindingDescription *desc =
|
|
&vi_info->pVertexBindingDescriptions[i];
|
|
|
|
pipeline->binding_stride[desc->binding] = desc->stride;
|
|
|
|
/* Step rate is programmed per vertex element (attribute), not
|
|
* binding. Set up a map of which bindings step per instance, for
|
|
* reference by vertex element setup. */
|
|
switch (desc->inputRate) {
|
|
default:
|
|
case VK_VERTEX_INPUT_RATE_VERTEX:
|
|
pipeline->instancing_enable[desc->binding] = false;
|
|
break;
|
|
case VK_VERTEX_INPUT_RATE_INSTANCE:
|
|
pipeline->instancing_enable[desc->binding] = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
const VkPipelineInputAssemblyStateCreateInfo *ia_info =
|
|
pCreateInfo->pInputAssemblyState;
|
|
pipeline->primitive_restart = ia_info->primitiveRestartEnable;
|
|
pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
|
|
|
|
return VK_SUCCESS;
|
|
|
|
compile_fail:
|
|
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
|
|
if (pipeline->shaders[s])
|
|
anv_shader_bin_unref(device, pipeline->shaders[s]);
|
|
}
|
|
|
|
anv_reloc_list_finish(&pipeline->batch_relocs, alloc);
|
|
|
|
return result;
|
|
}
|
|
|
|
VkResult
|
|
anv_graphics_pipeline_create(
|
|
VkDevice _device,
|
|
VkPipelineCache _cache,
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
|
const VkAllocationCallbacks *pAllocator,
|
|
VkPipeline *pPipeline)
|
|
{
|
|
ANV_FROM_HANDLE(anv_device, device, _device);
|
|
ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
|
|
|
|
switch (device->info.gen) {
|
|
case 7:
|
|
if (device->info.is_haswell)
|
|
return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
else
|
|
return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
case 8:
|
|
return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
case 9:
|
|
return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
default:
|
|
unreachable("unsupported gen\n");
|
|
}
|
|
}
|
|
|
|
VkResult anv_CreateGraphicsPipelines(
|
|
VkDevice _device,
|
|
VkPipelineCache pipelineCache,
|
|
uint32_t count,
|
|
const VkGraphicsPipelineCreateInfo* pCreateInfos,
|
|
const VkAllocationCallbacks* pAllocator,
|
|
VkPipeline* pPipelines)
|
|
{
|
|
VkResult result = VK_SUCCESS;
|
|
|
|
unsigned i = 0;
|
|
for (; i < count; i++) {
|
|
result = anv_graphics_pipeline_create(_device,
|
|
pipelineCache,
|
|
&pCreateInfos[i],
|
|
pAllocator, &pPipelines[i]);
|
|
if (result != VK_SUCCESS) {
|
|
for (unsigned j = 0; j < i; j++) {
|
|
anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
}
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
static VkResult anv_compute_pipeline_create(
|
|
VkDevice _device,
|
|
VkPipelineCache _cache,
|
|
const VkComputePipelineCreateInfo* pCreateInfo,
|
|
const VkAllocationCallbacks* pAllocator,
|
|
VkPipeline* pPipeline)
|
|
{
|
|
ANV_FROM_HANDLE(anv_device, device, _device);
|
|
ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
|
|
|
|
switch (device->info.gen) {
|
|
case 7:
|
|
if (device->info.is_haswell)
|
|
return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
else
|
|
return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
case 8:
|
|
return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
case 9:
|
|
return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
|
|
default:
|
|
unreachable("unsupported gen\n");
|
|
}
|
|
}
|
|
|
|
VkResult anv_CreateComputePipelines(
|
|
VkDevice _device,
|
|
VkPipelineCache pipelineCache,
|
|
uint32_t count,
|
|
const VkComputePipelineCreateInfo* pCreateInfos,
|
|
const VkAllocationCallbacks* pAllocator,
|
|
VkPipeline* pPipelines)
|
|
{
|
|
VkResult result = VK_SUCCESS;
|
|
|
|
unsigned i = 0;
|
|
for (; i < count; i++) {
|
|
result = anv_compute_pipeline_create(_device, pipelineCache,
|
|
&pCreateInfos[i],
|
|
pAllocator, &pPipelines[i]);
|
|
if (result != VK_SUCCESS) {
|
|
for (unsigned j = 0; j < i; j++) {
|
|
anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
}
|
|
|
|
return VK_SUCCESS;
|
|
}
|