5809209316
We have a couple of checks where we allow this to be NULL, but later we unconditionally and unavoidably dereference the pointer, which means there's no way that it ever could have been NULL. Change the assert at the top to not allow NULL, and remove checks for it being NULL CID: 1616544 Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31156>
722 lines
29 KiB
C
722 lines
29 KiB
C
/*
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* Copyright © 2023 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "util/macros.h"
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "common/intel_compute_slm.h"
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#include "common/intel_genX_state_brw.h"
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static void
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genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
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{
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assert(state->cmd_buffer && state->cmd_buffer->state.current_pipeline == _3D);
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struct anv_batch *batch = state->batch;
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struct anv_device *device = state->device;
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const struct brw_wm_prog_data *prog_data =
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brw_wm_prog_data_const(state->kernel->prog_data);
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uint32_t *dw = anv_batch_emitn(batch,
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1 + 2 * GENX(VERTEX_ELEMENT_STATE_length),
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GENX(3DSTATE_VERTEX_ELEMENTS));
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/* You might think there is some shady stuff going here and you would be
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* right. We're setting up 2 VERTEX_ELEMENT_STATE yet we're only providing
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* 1 (positions) VERTEX_BUFFER_STATE later.
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*
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* Find more about how to set up a 3D pipeline with a fragment shader but
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* without a vertex shader in blorp_emit_vertex_elements() in
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* blorp_genX_exec_brw.h.
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*/
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GENX(VERTEX_ELEMENT_STATE_pack)(
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batch, dw + 1, &(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 1,
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.Valid = true,
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.SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
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.SourceElementOffset = 0,
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.Component0Control = VFCOMP_STORE_SRC,
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.Component1Control = VFCOMP_STORE_0,
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.Component2Control = VFCOMP_STORE_0,
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.Component3Control = VFCOMP_STORE_0,
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});
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GENX(VERTEX_ELEMENT_STATE_pack)(
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batch, dw + 3, &(struct GENX(VERTEX_ELEMENT_STATE)) {
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.VertexBufferIndex = 0,
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.Valid = true,
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.SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT,
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.SourceElementOffset = 0,
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.Component0Control = VFCOMP_STORE_SRC,
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.Component1Control = VFCOMP_STORE_SRC,
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.Component2Control = VFCOMP_STORE_SRC,
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.Component3Control = VFCOMP_STORE_1_FP,
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});
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anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf);
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anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs) {
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sgvs.InstanceIDEnable = true;
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sgvs.InstanceIDComponentNumber = COMP_1;
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sgvs.InstanceIDElementOffset = 0;
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}
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#if GFX_VER >= 11
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anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS_2), sgvs);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
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vfi.InstancingEnable = false;
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vfi.VertexElementIndex = 0;
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}
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anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
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vfi.InstancingEnable = false;
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vfi.VertexElementIndex = 1;
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}
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anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
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topo.PrimitiveTopologyType = _3DPRIM_RECTLIST;
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}
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/* Emit URB setup. We tell it that the VS is active because we want it to
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* allocate space for the VS. Even though one isn't run, we need VUEs to
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* store the data that VF is going to pass to SOL.
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*/
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struct intel_urb_config urb_cfg_out = {
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.size = { DIV_ROUND_UP(32, 64), 1, 1, 1 },
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};
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genX(emit_l3_config)(batch, device, state->l3_config);
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state->cmd_buffer->state.current_l3_config = state->l3_config;
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enum intel_urb_deref_block_size deref_block_size;
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genX(emit_urb_setup)(device, batch, state->l3_config,
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VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_FRAGMENT_BIT,
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state->urb_cfg, &urb_cfg_out, &deref_block_size);
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anv_batch_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) {
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ps_blend.HasWriteableRT = true;
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}
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anv_batch_emit(batch, GENX(3DSTATE_WM_DEPTH_STENCIL), wm);
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#if GFX_VER >= 12
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anv_batch_emit(batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
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db.DepthBoundsTestEnable = false;
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db.DepthBoundsTestMinValue = 0.0;
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db.DepthBoundsTestMaxValue = 1.0;
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}
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms);
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anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
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sm.SampleMask = 0x1;
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}
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anv_batch_emit(batch, GENX(3DSTATE_VS), vs);
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anv_batch_emit(batch, GENX(3DSTATE_HS), hs);
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anv_batch_emit(batch, GENX(3DSTATE_TE), te);
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anv_batch_emit(batch, GENX(3DSTATE_DS), DS);
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#if GFX_VERx10 >= 125
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if (device->vk.enabled_extensions.EXT_mesh_shader) {
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anv_batch_emit(batch, GENX(3DSTATE_MESH_CONTROL), mesh);
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anv_batch_emit(batch, GENX(3DSTATE_TASK_CONTROL), task);
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}
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so);
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anv_batch_emit(batch, GENX(3DSTATE_GS), gs);
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anv_batch_emit(batch, GENX(3DSTATE_CLIP), clip) {
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clip.PerspectiveDivideDisable = true;
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}
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anv_batch_emit(batch, GENX(3DSTATE_SF), sf) {
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#if GFX_VER >= 12
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sf.DerefBlockSize = deref_block_size;
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#endif
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}
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anv_batch_emit(batch, GENX(3DSTATE_RASTER), raster) {
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raster.CullMode = CULLMODE_NONE;
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}
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anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) {
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sbe.VertexURBEntryReadOffset = 1;
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sbe.NumberofSFOutputAttributes = prog_data->num_varying_inputs;
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sbe.VertexURBEntryReadLength = MAX2((prog_data->num_varying_inputs + 1) / 2, 1);
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sbe.ConstantInterpolationEnable = prog_data->flat_inputs;
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sbe.ForceVertexURBEntryReadLength = true;
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sbe.ForceVertexURBEntryReadOffset = true;
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for (unsigned i = 0; i < 32; i++)
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sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
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}
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anv_batch_emit(batch, GENX(3DSTATE_WM), wm);
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anv_batch_emit(batch, GENX(3DSTATE_PS), ps) {
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intel_set_ps_dispatch_state(&ps, device->info, prog_data,
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1 /* rasterization_samples */,
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0 /* msaa_flags */);
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ps.VectorMaskEnable = prog_data->uses_vmask;
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ps.BindingTableEntryCount = GFX_VER == 9 ? 1 : 0;
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#if GFX_VER < 20
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ps.PushConstantEnable = prog_data->base.nr_params > 0 ||
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prog_data->base.ubo_ranges[0].length;
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#endif
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
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#if GFX_VER < 20
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
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#endif
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ps.KernelStartPointer0 = state->kernel->kernel.offset +
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brw_wm_prog_data_prog_offset(prog_data, ps, 0);
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ps.KernelStartPointer1 = state->kernel->kernel.offset +
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brw_wm_prog_data_prog_offset(prog_data, ps, 1);
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#if GFX_VER < 20
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ps.KernelStartPointer2 = state->kernel->kernel.offset +
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brw_wm_prog_data_prog_offset(prog_data, ps, 2);
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#endif
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ps.MaximumNumberofThreadsPerPSD = device->info->max_threads_per_psd - 1;
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}
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#if INTEL_WA_18038825448_GFX_VER
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const bool needs_ps_dependency =
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genX(cmd_buffer_set_coarse_pixel_active)
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(state->cmd_buffer, ANV_COARSE_PIXEL_STATE_DISABLED);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_PS_EXTRA), psx) {
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psx.PixelShaderValid = true;
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#if GFX_VER < 20
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psx.AttributeEnable = prog_data->num_varying_inputs > 0;
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#endif
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psx.PixelShaderIsPerSample = prog_data->persample_dispatch;
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psx.PixelShaderComputedDepthMode = prog_data->computed_depth_mode;
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psx.PixelShaderComputesStencil = prog_data->computed_stencil;
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#if INTEL_WA_18038825448_GFX_VER
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psx.EnablePSDependencyOnCPsizeChange = needs_ps_dependency;
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#endif
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}
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anv_batch_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
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struct anv_state cc_state =
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anv_state_stream_alloc(state->dynamic_state_stream,
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4 * GENX(CC_VIEWPORT_length), 32);
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if (cc_state.map == NULL)
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return;
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struct GENX(CC_VIEWPORT) cc_viewport = {
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.MinimumDepth = 0.0f,
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.MaximumDepth = 1.0f,
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};
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GENX(CC_VIEWPORT_pack)(NULL, cc_state.map, &cc_viewport);
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cc.CCViewportPointer = cc_state.offset;
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}
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#if GFX_VER >= 12
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/* Disable Primitive Replication. */
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anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
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#endif
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anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc);
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anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_HS), alloc);
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anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_DS), alloc);
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anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS), alloc);
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anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
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alloc.ConstantBufferOffset = 0;
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alloc.ConstantBufferSize = device->info->max_constant_urb_size_kb;
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}
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#if GFX_VERx10 == 125
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/* DG2: Wa_22011440098
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* MTL: Wa_18022330953
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*
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* In 3D mode, after programming push constant alloc command immediately
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* program push constant command(ZERO length) without any commit between
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* them.
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*
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* Note that Wa_16011448509 isn't needed here as all address bits are zero.
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*/
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anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_ALL), c) {
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/* Update empty push constants for all stages (bitmask = 11111b) */
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c.ShaderUpdateEnable = 0x1f;
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c.MOCS = anv_mocs(device, NULL, 0);
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}
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#endif
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#if GFX_VER == 9
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/* Allocate a binding table for Gfx9 for 2 reason :
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*
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* 1. we need a to emit a 3DSTATE_BINDING_TABLE_POINTERS_PS to make the
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* HW apply the preceeding 3DSTATE_CONSTANT_PS
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*
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* 2. Emitting an empty 3DSTATE_BINDING_TABLE_POINTERS_PS would cause RT
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* writes (even though they're empty) to disturb later writes
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* (probably due to RT cache)
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*
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* Our binding table only has one entry to the null surface.
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*/
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uint32_t bt_offset;
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state->bt_state =
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anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
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if (state->bt_state.map == NULL) {
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VkResult result = anv_cmd_buffer_new_binding_table_block(state->cmd_buffer);
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if (result != VK_SUCCESS)
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return;
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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genX(cmd_buffer_emit_bt_pool_base_address)(state->cmd_buffer);
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state->bt_state =
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anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
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assert(state->bt_state.map != NULL);
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}
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uint32_t *bt_map = state->bt_state.map;
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bt_map[0] = anv_bindless_state_for_binding_table(
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device,
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device->null_surface_state).offset + bt_offset;
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state->cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
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#endif
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#if INTEL_WA_14018283232_GFX_VER
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genX(cmd_buffer_ensure_wa_14018283232)(state->cmd_buffer, false);
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#endif
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/* Flag all the instructions emitted by the memcpy. */
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struct anv_gfx_dynamic_state *hw_state =
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&state->cmd_buffer->state.gfx.dyn_state;
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS);
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#if GFX_VER >= 11
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2);
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#endif
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#if GFX_VER >= 12
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
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#endif
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DEPTH_BOUNDS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_EXTRA);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND);
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if (device->vk.enabled_extensions.EXT_mesh_shader) {
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL);
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BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL);
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}
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/* Update urb config after simple shader. */
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memcpy(&state->cmd_buffer->state.gfx.urb_cfg, &urb_cfg_out,
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sizeof(struct intel_urb_config));
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state->cmd_buffer->state.gfx.vb_dirty = BITFIELD_BIT(0);
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state->cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_INDEX_BUFFER |
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ANV_CMD_DIRTY_XFB_ENABLE |
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ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE |
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ANV_CMD_DIRTY_FS_MSAA_FLAGS |
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ANV_CMD_DIRTY_RESTART_INDEX);
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state->cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
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state->cmd_buffer->state.gfx.push_constant_stages = VK_SHADER_STAGE_FRAGMENT_BIT;
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}
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static void
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genX(emit_simpler_shader_init_compute)(struct anv_simple_shader *state)
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{
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assert(state->cmd_buffer == NULL ||
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state->cmd_buffer->state.current_pipeline == GPGPU);
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#if GFX_VERx10 >= 125
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struct anv_shader_bin *cs_bin = state->kernel;
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const struct brw_cs_prog_data *prog_data =
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(const struct brw_cs_prog_data *) cs_bin->prog_data;
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/* Currently our simple shaders are simple enough that they never spill. */
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assert(prog_data->base.total_scratch == 0);
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if (state->cmd_buffer != NULL) {
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genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, 0);
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} else {
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anv_batch_emit(state->batch, GENX(CFE_STATE), cfe) {
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cfe.MaximumNumberofThreads =
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state->device->info->max_cs_threads *
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state->device->info->subslice_total;
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}
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}
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#endif
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}
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/** Initialize a simple shader emission */
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void
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genX(emit_simple_shader_init)(struct anv_simple_shader *state)
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{
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assert(state->kernel->stage == MESA_SHADER_FRAGMENT ||
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state->kernel->stage == MESA_SHADER_COMPUTE);
|
|
|
|
if (state->kernel->stage == MESA_SHADER_FRAGMENT)
|
|
genX(emit_simpler_shader_init_fragment)(state);
|
|
else
|
|
genX(emit_simpler_shader_init_compute)(state);
|
|
}
|
|
|
|
/** Allocate push constant data for a simple shader */
|
|
struct anv_state
|
|
genX(simple_shader_alloc_push)(struct anv_simple_shader *state, uint32_t size)
|
|
{
|
|
struct anv_state s;
|
|
|
|
if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
|
|
s = anv_state_stream_alloc(state->dynamic_state_stream,
|
|
size, ANV_UBO_ALIGNMENT);
|
|
} else {
|
|
#if GFX_VERx10 >= 125
|
|
s = anv_state_stream_alloc(state->general_state_stream, align(size, 64), 64);
|
|
#else
|
|
s = anv_state_stream_alloc(state->dynamic_state_stream, size, 64);
|
|
#endif
|
|
}
|
|
|
|
if (s.map == NULL)
|
|
anv_batch_set_error(state->batch, VK_ERROR_OUT_OF_DEVICE_MEMORY);
|
|
|
|
return s;
|
|
}
|
|
|
|
/** Get the address of allocated push constant data by
|
|
* genX(simple_shader_alloc_push)
|
|
*/
|
|
struct anv_address
|
|
genX(simple_shader_push_state_address)(struct anv_simple_shader *state,
|
|
struct anv_state push_state)
|
|
{
|
|
if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
|
|
return anv_state_pool_state_address(
|
|
&state->device->dynamic_state_pool, push_state);
|
|
} else {
|
|
#if GFX_VERx10 >= 125
|
|
return anv_state_pool_state_address(
|
|
&state->device->general_state_pool, push_state);
|
|
#else
|
|
return anv_state_pool_state_address(
|
|
&state->device->dynamic_state_pool, push_state);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/** Emit a simple shader dispatch */
|
|
void
|
|
genX(emit_simple_shader_dispatch)(struct anv_simple_shader *state,
|
|
uint32_t num_threads,
|
|
struct anv_state push_state)
|
|
{
|
|
struct anv_device *device = state->device;
|
|
struct anv_batch *batch = state->batch;
|
|
struct anv_address push_addr =
|
|
anv_state_pool_state_address(&device->dynamic_state_pool, push_state);
|
|
|
|
if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
|
|
/* At the moment we require a command buffer associated with this
|
|
* emission as we need to allocate binding tables on Gfx9.
|
|
*/
|
|
assert(state->cmd_buffer != NULL);
|
|
|
|
struct anv_state vs_data_state =
|
|
anv_state_stream_alloc(state->dynamic_state_stream,
|
|
9 * sizeof(uint32_t), 32);
|
|
if (vs_data_state.map == NULL)
|
|
return;
|
|
|
|
float x0 = 0.0f, x1 = MIN2(num_threads, 8192);
|
|
float y0 = 0.0f, y1 = DIV_ROUND_UP(num_threads, 8192);
|
|
float z = 0.0f;
|
|
|
|
float *vertices = vs_data_state.map;
|
|
vertices[0] = x1; vertices[1] = y1; vertices[2] = z; /* v0 */
|
|
vertices[3] = x0; vertices[4] = y1; vertices[5] = z; /* v1 */
|
|
vertices[6] = x0; vertices[7] = y0; vertices[8] = z; /* v2 */
|
|
|
|
uint32_t *dw = anv_batch_emitn(batch,
|
|
1 + GENX(VERTEX_BUFFER_STATE_length),
|
|
GENX(3DSTATE_VERTEX_BUFFERS));
|
|
GENX(VERTEX_BUFFER_STATE_pack)(batch, dw + 1,
|
|
&(struct GENX(VERTEX_BUFFER_STATE)) {
|
|
.VertexBufferIndex = 0,
|
|
.AddressModifyEnable = true,
|
|
.BufferStartingAddress = (struct anv_address) {
|
|
.bo = device->dynamic_state_pool.block_pool.bo,
|
|
.offset = vs_data_state.offset,
|
|
},
|
|
.BufferPitch = 3 * sizeof(float),
|
|
.BufferSize = 9 * sizeof(float),
|
|
.MOCS = anv_mocs(device, NULL, 0),
|
|
#if GFX_VER >= 12
|
|
.L3BypassDisable = true,
|
|
#endif
|
|
});
|
|
|
|
#if GFX_VERx10 > 120
|
|
dw =
|
|
anv_batch_emitn(batch,
|
|
GENX(3DSTATE_CONSTANT_ALL_length) +
|
|
GENX(3DSTATE_CONSTANT_ALL_DATA_length),
|
|
GENX(3DSTATE_CONSTANT_ALL),
|
|
.ShaderUpdateEnable = BITFIELD_BIT(MESA_SHADER_FRAGMENT),
|
|
.PointerBufferMask = 0x1,
|
|
.MOCS = anv_mocs(device, NULL, 0));
|
|
|
|
GENX(3DSTATE_CONSTANT_ALL_DATA_pack)(
|
|
batch, dw + GENX(3DSTATE_CONSTANT_ALL_length),
|
|
&(struct GENX(3DSTATE_CONSTANT_ALL_DATA)) {
|
|
.PointerToConstantBuffer = push_addr,
|
|
.ConstantBufferReadLength = DIV_ROUND_UP(push_state.alloc_size, 32),
|
|
});
|
|
#else
|
|
/* The Skylake PRM contains the following restriction:
|
|
*
|
|
* "The driver must ensure The following case does not occur
|
|
* without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
|
|
* buffer 3 read length equal to zero committed followed by a
|
|
* 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
|
|
* zero committed."
|
|
*
|
|
* To avoid this, we program the highest slot.
|
|
*/
|
|
anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_PS), c) {
|
|
c.MOCS = anv_mocs(device, NULL, 0);
|
|
c.ConstantBody.ReadLength[3] = DIV_ROUND_UP(push_state.alloc_size, 32);
|
|
c.ConstantBody.Buffer[3] = push_addr;
|
|
}
|
|
#endif
|
|
|
|
#if GFX_VER == 9
|
|
/* Why are the push constants not flushed without a binding table
|
|
* update??
|
|
*/
|
|
anv_batch_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS), btp) {
|
|
btp.PointertoPSBindingTable = state->bt_state.offset;
|
|
}
|
|
#endif
|
|
|
|
genX(emit_breakpoint)(batch, device, true);
|
|
anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) {
|
|
prim.VertexAccessType = SEQUENTIAL;
|
|
prim.PrimitiveTopologyType = _3DPRIM_RECTLIST;
|
|
prim.VertexCountPerInstance = 3;
|
|
prim.InstanceCount = 1;
|
|
}
|
|
genX(batch_emit_post_3dprimitive_was)(batch, device, _3DPRIM_RECTLIST, 3);
|
|
genX(emit_breakpoint)(batch, device, false);
|
|
} else {
|
|
const struct intel_device_info *devinfo = device->info;
|
|
const struct brw_cs_prog_data *prog_data =
|
|
(const struct brw_cs_prog_data *) state->kernel->prog_data;
|
|
const struct intel_cs_dispatch_info dispatch =
|
|
brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
|
|
|
|
#if GFX_VERx10 >= 125
|
|
anv_batch_emit(batch, GENX(COMPUTE_WALKER), cw) {
|
|
cw.SIMDSize = dispatch.simd_size / 16;
|
|
cw.MessageSIMD = dispatch.simd_size / 16,
|
|
cw.IndirectDataStartAddress = push_state.offset;
|
|
cw.IndirectDataLength = push_state.alloc_size;
|
|
cw.LocalXMaximum = prog_data->local_size[0] - 1;
|
|
cw.LocalYMaximum = prog_data->local_size[1] - 1;
|
|
cw.LocalZMaximum = prog_data->local_size[2] - 1;
|
|
cw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
|
|
dispatch.simd_size);
|
|
cw.ThreadGroupIDYDimension = 1;
|
|
cw.ThreadGroupIDZDimension = 1;
|
|
cw.ExecutionMask = dispatch.right_mask;
|
|
cw.PostSync.MOCS = anv_mocs(device, NULL, 0);
|
|
|
|
#if GFX_VERx10 >= 125
|
|
cw.GenerateLocalID = prog_data->generate_local_id != 0;
|
|
cw.EmitLocal = prog_data->generate_local_id;
|
|
cw.WalkOrder = prog_data->walk_order;
|
|
cw.TileLayout = prog_data->walk_order == INTEL_WALK_ORDER_YXZ ?
|
|
TileY32bpe : Linear;
|
|
#endif
|
|
|
|
cw.InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) {
|
|
.KernelStartPointer = state->kernel->kernel.offset +
|
|
brw_cs_prog_data_prog_offset(prog_data,
|
|
dispatch.simd_size),
|
|
.SamplerStatePointer = 0,
|
|
.BindingTablePointer = 0,
|
|
.BindingTableEntryCount = 0,
|
|
.NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
|
|
.SharedLocalMemorySize = intel_compute_slm_encode_size(GFX_VER,
|
|
prog_data->base.total_shared),
|
|
.NumberOfBarriers = prog_data->uses_barrier,
|
|
};
|
|
}
|
|
#else
|
|
const uint32_t vfe_curbe_allocation =
|
|
ALIGN(prog_data->push.per_thread.regs * dispatch.threads +
|
|
prog_data->push.cross_thread.regs, 2);
|
|
|
|
/* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
|
|
*
|
|
* "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
|
|
* the only bits that are changed are scoreboard related: Scoreboard
|
|
* Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
|
|
* these scoreboard related states, a MEDIA_STATE_FLUSH is
|
|
* sufficient."
|
|
*/
|
|
enum anv_pipe_bits emitted_bits = 0;
|
|
genX(emit_apply_pipe_flushes)(batch, device, GPGPU, ANV_PIPE_CS_STALL_BIT,
|
|
&emitted_bits);
|
|
|
|
/* If we have a command buffer allocated with the emission, update the
|
|
* pending bits.
|
|
*/
|
|
if (state->cmd_buffer)
|
|
anv_cmd_buffer_update_pending_query_bits(state->cmd_buffer, emitted_bits);
|
|
|
|
anv_batch_emit(batch, GENX(MEDIA_VFE_STATE), vfe) {
|
|
vfe.StackSize = 0;
|
|
vfe.MaximumNumberofThreads =
|
|
devinfo->max_cs_threads * devinfo->subslice_total - 1;
|
|
vfe.NumberofURBEntries = 2;
|
|
#if GFX_VER < 11
|
|
vfe.ResetGatewayTimer = true;
|
|
#endif
|
|
vfe.URBEntryAllocationSize = 2;
|
|
vfe.CURBEAllocationSize = vfe_curbe_allocation;
|
|
|
|
if (prog_data->base.total_scratch) {
|
|
/* Broadwell's Per Thread Scratch Space is in the range [0, 11]
|
|
* where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
|
|
*/
|
|
vfe.PerThreadScratchSpace =
|
|
ffs(prog_data->base.total_scratch) - 11;
|
|
vfe.ScratchSpaceBasePointer =
|
|
(struct anv_address) {
|
|
.bo = anv_scratch_pool_alloc(device,
|
|
&device->scratch_pool,
|
|
MESA_SHADER_COMPUTE,
|
|
prog_data->base.total_scratch),
|
|
.offset = 0,
|
|
};
|
|
}
|
|
}
|
|
struct anv_state iface_desc_state =
|
|
anv_state_stream_alloc(state->dynamic_state_stream,
|
|
GENX(INTERFACE_DESCRIPTOR_DATA_length) * 4, 64);
|
|
if (iface_desc_state.map == NULL)
|
|
return;
|
|
|
|
struct GENX(INTERFACE_DESCRIPTOR_DATA) iface_desc = {
|
|
.KernelStartPointer = state->kernel->kernel.offset +
|
|
brw_cs_prog_data_prog_offset(prog_data,
|
|
dispatch.simd_size),
|
|
|
|
.SamplerCount = 0,
|
|
.BindingTableEntryCount = 0,
|
|
.BarrierEnable = prog_data->uses_barrier,
|
|
.SharedLocalMemorySize = intel_compute_slm_encode_size(GFX_VER,
|
|
prog_data->base.total_shared),
|
|
|
|
.ConstantURBEntryReadOffset = 0,
|
|
.ConstantURBEntryReadLength = prog_data->push.per_thread.regs,
|
|
.CrossThreadConstantDataReadLength = prog_data->push.cross_thread.regs,
|
|
#if GFX_VER >= 12
|
|
/* TODO: Check if we are missing workarounds and enable mid-thread
|
|
* preemption.
|
|
*
|
|
* We still have issues with mid-thread preemption (it was already
|
|
* disabled by the kernel on gfx11, due to missing workarounds). It's
|
|
* possible that we are just missing some workarounds, and could
|
|
* enable it later, but for now let's disable it to fix a GPU in
|
|
* compute in Car Chase (and possibly more).
|
|
*/
|
|
.ThreadPreemptionDisable = true,
|
|
#endif
|
|
.NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
|
|
};
|
|
GENX(INTERFACE_DESCRIPTOR_DATA_pack)(batch, iface_desc_state.map, &iface_desc);
|
|
anv_batch_emit(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
|
|
mid.InterfaceDescriptorTotalLength = iface_desc_state.alloc_size;
|
|
mid.InterfaceDescriptorDataStartAddress = iface_desc_state.offset;
|
|
}
|
|
anv_batch_emit(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
|
|
curbe.CURBEDataStartAddress = push_state.offset;
|
|
curbe.CURBETotalDataLength = push_state.alloc_size;
|
|
}
|
|
anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
|
|
ggw.SIMDSize = dispatch.simd_size / 16;
|
|
ggw.ThreadDepthCounterMaximum = 0;
|
|
ggw.ThreadHeightCounterMaximum = 0;
|
|
ggw.ThreadWidthCounterMaximum = dispatch.threads - 1;
|
|
ggw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
|
|
dispatch.simd_size);
|
|
ggw.ThreadGroupIDYDimension = 1;
|
|
ggw.ThreadGroupIDZDimension = 1;
|
|
ggw.RightExecutionMask = dispatch.right_mask;
|
|
ggw.BottomExecutionMask = 0xffffffff;
|
|
}
|
|
anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH), msf);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void
|
|
genX(emit_simple_shader_end)(struct anv_simple_shader *state)
|
|
{
|
|
anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
|
|
|
|
if ((state->batch->next - state->batch->start) & 4)
|
|
anv_batch_emit(state->batch, GENX(MI_NOOP), noop);
|
|
}
|