
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
507 lines
20 KiB
C
507 lines
20 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "genX_pipeline_util.h"
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static void
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emit_ia_state(struct anv_pipeline *pipeline,
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const VkPipelineInputAssemblyStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
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vft.PrimitiveTopologyType = pipeline->topology;
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}
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}
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static void
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emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterizationStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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uint32_t samples = 1;
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if (ms_info)
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samples = ms_info->rasterizationSamples;
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.ViewportTransformEnable = !(extra && extra->use_rectlist),
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 1,
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.PointWidthSource = Vertex,
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.PointWidth = 1.0,
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};
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/* FINISHME: VkBool32 rasterizerDiscardEnable; */
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GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
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struct GENX(3DSTATE_RASTER) raster = {
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GENX(3DSTATE_RASTER_header),
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/* For details on 3DSTATE_RASTER multisample state, see the BSpec table
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* "Multisample Modes State".
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*/
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.DXMultisampleRasterizationEnable = samples > 1,
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.ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
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.ForceMultisampling = false,
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.FrontWinding = vk_to_gen_front_face[info->frontFace],
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.CullMode = vk_to_gen_cullmode[info->cullMode],
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.FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.ScissorRectangleEnable = !(extra && extra->use_rectlist),
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#if GEN_GEN == 8
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.ViewportZClipTestEnable = true,
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#else
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/* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
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.ViewportZFarClipTestEnable = true,
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.ViewportZNearClipTestEnable = true,
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#endif
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.GlobalDepthOffsetEnableSolid = info->depthBiasEnable,
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.GlobalDepthOffsetEnableWireframe = info->depthBiasEnable,
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.GlobalDepthOffsetEnablePoint = info->depthBiasEnable,
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};
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GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
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}
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static void
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emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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uint32_t num_dwords = GENX(BLEND_STATE_length);
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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};
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/* Default everything to disabled */
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for (uint32_t i = 0; i < 8; i++) {
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blend_state.Entry[i].WriteDisableAlpha = true;
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blend_state.Entry[i].WriteDisableRed = true;
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blend_state.Entry[i].WriteDisableGreen = true;
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blend_state.Entry[i].WriteDisableBlue = true;
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}
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struct anv_pipeline_bind_map *map =
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&pipeline->bindings[MESA_SHADER_FRAGMENT];
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bool has_writeable_rt = false;
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for (unsigned i = 0; i < map->surface_count; i++) {
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struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
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/* All color attachments are at the beginning of the binding table */
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if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
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break;
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/* We can have at most 8 attachments */
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assert(i < 8);
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if (binding->offset >= info->attachmentCount)
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continue;
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const VkPipelineColorBlendAttachmentState *a =
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&info->pAttachments[binding->offset];
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if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
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a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
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a->colorBlendOp != a->alphaBlendOp) {
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blend_state.IndependentAlphaBlendEnable = true;
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}
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blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.PreBlendSourceOnlyClampEnable = false,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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};
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if (a->colorWriteMask != 0)
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has_writeable_rt = true;
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->colorBlendOp == VK_BLEND_OP_MIN ||
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a->colorBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
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a->alphaBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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}
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struct GENX(BLEND_STATE_ENTRY) *bs0 = &blend_state.Entry[0];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
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blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable;
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blend.HasWriteableRT = has_writeable_rt;
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blend.ColorBufferBlendEnable = bs0->ColorBufferBlendEnable;
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blend.SourceAlphaBlendFactor = bs0->SourceAlphaBlendFactor;
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blend.DestinationAlphaBlendFactor = bs0->DestinationAlphaBlendFactor;
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blend.SourceBlendFactor = bs0->SourceBlendFactor;
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blend.DestinationBlendFactor = bs0->DestinationBlendFactor;
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blend.AlphaTestEnable = false;
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blend.IndependentAlphaBlendEnable =
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blend_state.IndependentAlphaBlendEnable;
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}
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
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if (!device->info.has_llc)
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anv_state_clflush(pipeline->blend_state);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = pipeline->blend_state.offset;
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bsp.BlendStatePointerValid = true;
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}
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}
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static void
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emit_ms_state(struct anv_pipeline *pipeline,
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const VkPipelineMultisampleStateCreateInfo *info)
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{
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uint32_t samples = 1;
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uint32_t log2_samples = 0;
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/* From the Vulkan 1.0 spec:
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* If pSampleMask is NULL, it is treated as if the mask has all bits
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* enabled, i.e. no coverage is removed from fragments.
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*
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* 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
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*/
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uint32_t sample_mask = 0xffff;
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if (info) {
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samples = info->rasterizationSamples;
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log2_samples = __builtin_ffs(samples) - 1;
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}
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if (info && info->pSampleMask)
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sample_mask &= info->pSampleMask[0];
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if (info && info->sampleShadingEnable)
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anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
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/* The PRM says that this bit is valid only for DX9:
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*
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* SW can choose to set this bit only for DX9 API. DX10/OGL API's
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* should not have any effect by setting or not setting this bit.
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*/
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ms.PixelPositionOffsetEnable = false;
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ms.PixelLocation = CENTER;
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ms.NumberofMultisamples = log2_samples;
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}
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
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sm.SampleMask = sample_mask;
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}
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}
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VkResult
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genX(graphics_pipeline_create)(
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VkDevice _device,
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struct anv_pipeline_cache * cache,
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const VkGraphicsPipelineCreateInfo* pCreateInfo,
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const struct anv_graphics_pipeline_create_info *extra,
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const VkAllocationCallbacks* pAllocator,
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
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struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
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struct anv_pipeline *pipeline;
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VkResult result;
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uint32_t offset, length;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
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pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (pipeline == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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result = anv_pipeline_init(pipeline, device, cache,
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pCreateInfo, extra, pAllocator);
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if (result != VK_SUCCESS) {
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anv_free2(&device->alloc, pAllocator, pipeline);
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return result;
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}
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assert(pCreateInfo->pVertexInputState);
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emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
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assert(pCreateInfo->pInputAssemblyState);
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emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
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assert(pCreateInfo->pRasterizationState);
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emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
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pCreateInfo->pMultisampleState, extra);
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emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
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emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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emit_urb_setup(pipeline);
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const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP), clip) {
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clip.ClipEnable = !(extra && extra->use_rectlist);
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clip.EarlyCullEnable = true;
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clip.APIMode = 1; /* D3D */
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clip.ViewportXYClipTestEnable = true;
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clip.ClipMode =
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pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
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REJECT_ALL : NORMAL;
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clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
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(wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
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clip.TriangleStripListProvokingVertexSelect = 0;
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clip.LineStripListProvokingVertexSelect = 0;
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clip.TriangleFanProvokingVertexSelect = 1;
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clip.MinimumPointWidth = 0.125;
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clip.MaximumPointWidth = 255.875;
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clip.MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1;
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}
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
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wm.StatisticsEnable = true;
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wm.LineEndCapAntialiasingRegionWidth = _05pixels;
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wm.LineAntialiasingRegionWidth = _10pixels;
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wm.EarlyDepthStencilControl = NORMAL;
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wm.ForceThreadDispatchEnable = NORMAL;
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wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
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wm.BarycentricInterpolationMode = pipeline->ps_ksp0 == NO_KERNEL ?
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0 : wm_prog_data->barycentric_interp_modes;
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}
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if (pipeline->gs_kernel == NO_KERNEL) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
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} else {
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const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
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offset = 1;
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length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
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gs.SingleProgramFlow = false;
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gs.KernelStartPointer = pipeline->gs_kernel;
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gs.VectorMaskEnable = false;
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gs.SamplerCount = 0;
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gs.BindingTableEntryCount = 0;
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gs.ExpectedVertexCount = gs_prog_data->vertices_in;
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gs.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY];
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gs.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base);
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gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
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gs.OutputTopology = gs_prog_data->output_topology;
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gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
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gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
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gs.DispatchGRFStartRegisterForURBData =
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gs_prog_data->base.base.dispatch_grf_start_reg;
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gs.MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1;
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gs.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords;
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gs.DispatchMode = gs_prog_data->base.dispatch_mode;
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gs.StatisticsEnable = true;
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gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
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gs.ReorderMode = TRAILING;
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gs.Enable = true;
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gs.ControlDataFormat = gs_prog_data->control_data_format;
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gs.StaticOutput = gs_prog_data->static_vertex_count >= 0;
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gs.StaticOutputVertexCount =
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gs_prog_data->static_vertex_count >= 0 ?
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gs_prog_data->static_vertex_count : 0;
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/* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
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* UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
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* UserClipDistanceCullTestEnableBitmask(v)
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*/
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gs.VertexURBEntryOutputReadOffset = offset;
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gs.VertexURBEntryOutputLength = length;
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}
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}
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const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
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/* Skip the VUE header and position slots */
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offset = 1;
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length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
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uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
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pipeline->vs_vec4;
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if (vs_start == NO_KERNEL || (extra && extra->disable_vs)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
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vs.FunctionEnable = false;
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/* Even if VS is disabled, SBE still gets the amount of
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* vertex data to read from this field. */
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vs.VertexURBEntryOutputReadOffset = offset;
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vs.VertexURBEntryOutputLength = length;
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}
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} else {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
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vs.KernelStartPointer = vs_start;
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vs.SingleVertexDispatch = false;
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vs.VectorMaskEnable = false;
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vs.SamplerCount = 0;
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vs.BindingTableEntryCount =
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vs_prog_data->base.base.binding_table.size_bytes / 4,
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vs.ThreadDispatchPriority = false;
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vs.FloatingPointMode = IEEE754;
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vs.IllegalOpcodeExceptionEnable = false;
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vs.AccessesUAV = false;
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vs.SoftwareExceptionEnable = false;
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vs.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
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vs.PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base);
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vs.DispatchGRFStartRegisterForURBData =
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vs_prog_data->base.base.dispatch_grf_start_reg;
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vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
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vs.VertexURBEntryReadOffset = 0;
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vs.MaximumNumberofThreads = device->info.max_vs_threads - 1;
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vs.StatisticsEnable = false;
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vs.SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL;
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vs.VertexCacheDisable = false;
|
|
vs.FunctionEnable = true;
|
|
|
|
vs.VertexURBEntryOutputReadOffset = offset;
|
|
vs.VertexURBEntryOutputLength = length;
|
|
|
|
/* TODO */
|
|
vs.UserClipDistanceClipTestEnableBitmask = 0;
|
|
vs.UserClipDistanceCullTestEnableBitmask = 0;
|
|
}
|
|
}
|
|
|
|
const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
|
|
if (pipeline->ps_ksp0 == NO_KERNEL) {
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
|
|
extra.PixelShaderValid = false;
|
|
}
|
|
} else {
|
|
emit_3dstate_sbe(pipeline);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
|
|
ps.KernelStartPointer0 = pipeline->ps_ksp0;
|
|
ps.KernelStartPointer1 = 0;
|
|
ps.KernelStartPointer2 = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
|
|
ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
|
|
ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
|
|
ps._32PixelDispatchEnable = false;
|
|
ps.SingleProgramFlow = false;
|
|
ps.VectorMaskEnable = true;
|
|
ps.SamplerCount = 1;
|
|
ps.PushConstantEnable = wm_prog_data->base.nr_params > 0;
|
|
ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
|
|
POSOFFSET_SAMPLE: POSOFFSET_NONE;
|
|
|
|
ps.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias;
|
|
|
|
ps.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT];
|
|
ps.PerThreadScratchSpace = scratch_space(&wm_prog_data->base);
|
|
|
|
ps.DispatchGRFStartRegisterForConstantSetupData0 =
|
|
wm_prog_data->base.dispatch_grf_start_reg;
|
|
ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
|
|
ps.DispatchGRFStartRegisterForConstantSetupData2 =
|
|
wm_prog_data->dispatch_grf_start_reg_2;
|
|
}
|
|
|
|
bool per_sample_ps = pCreateInfo->pMultisampleState &&
|
|
pCreateInfo->pMultisampleState->sampleShadingEnable;
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
|
|
ps.PixelShaderValid = true;
|
|
ps.PixelShaderKillsPixel = wm_prog_data->uses_kill;
|
|
ps.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
|
|
ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0;
|
|
ps.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
|
|
ps.PixelShaderIsPerSample = per_sample_ps;
|
|
ps.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
|
|
ps.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
|
|
#if GEN_GEN >= 9
|
|
ps.PixelShaderPullsBary = wm_prog_data->pulls_bary;
|
|
ps.InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
|
|
ICMS_INNER_CONSERVATIVE : ICMS_NONE;
|
|
#else
|
|
ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|