OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
4b4838b1ae46a0ce9fed88f275cc01167302cf24
third_party_mesa3d/src/intel/compiler
History
Francisco Jerez 4b4838b1ae Revert "i965/fs: Predicate byte scattered writes if needed" 
This reverts commit a4031bdfa9.  It's
redundant with the sample mask predication done at this point by the
common logical send lowering infrastructure, and rather buggy because
it wasn't applying the correct sample mask in shaders using discard,
since the dispatch mask returned by FS_OPCODE_MOV_DISPATCH_TO_FLAGS
doesn't reflect samples discarded by the shader, so it could have led
to data corruption in fragment shader invocations that execute discard
based on a non-dynamically uniform condition.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-03-02 11:28:56 -08:00
..
.gitignore
…
brw_cfg.cpp
intel/cfg: Represent divergent control flow paths caused by non-uniform loop execution.
2017-12-07 18:27:05 -08:00
brw_cfg.h
intel/compiler: consistently use ifndef guards over pragma once
2017-03-22 16:55:22 +00:00
brw_clip_line.c
i965: Move clip program compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_clip_point.c
i965: Move clip program compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_clip_tri.c
i965: Don't emit MOVs with undefined registers for Gen4 point clipping.
2018-02-28 15:03:51 -08:00
brw_clip_unfilled.c
i965: Move clip program compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_clip_util.c
i965: Move clip program compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_clip.h
i965: Move clip program compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_compile_clip.c
i965: Rewrite disassembly annotation code
2017-11-17 12:14:38 -08:00
brw_compile_sf.c
i965: Move SF compilation to the compiler
2017-05-26 07:58:01 -07:00
brw_compiler.c
intel/compiler: Re-add .vs_inputs_dual_locations = true
2018-02-28 13:25:21 -08:00
brw_compiler.h
i965: Drop render_target_start from binding table struct.
2018-01-22 10:03:52 -08:00
brw_dead_control_flow.cpp
…
brw_dead_control_flow.h
intel/compiler: consistently use ifndef guards over pragma once
2017-03-22 16:55:22 +00:00
brw_disasm_info.c
i965: Move mistakenly placed line
2018-02-05 09:50:56 -08:00
brw_disasm_info.h
i965: Stop including brw_cfg.h in brw_disasm_info.h
2017-11-17 21:51:16 -08:00
brw_disasm.c
intel/compiler: Add Gen11+ native float type
2018-02-28 11:15:47 -08:00
brw_eu_compact.c
intel/compiler: Add instruction compaction support on Gen11
2018-02-28 11:15:47 -08:00
brw_eu_defines.h
i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.
2017-12-30 20:30:34 -08:00
brw_eu_emit.c
intel/eu: Plumb header present bit to codegen helpers for HDC messages.
2018-03-02 11:28:56 -08:00
brw_eu_util.c
intel/compiler: whitespace cleanups
2017-03-13 11:16:35 +00:00
brw_eu_validate.c
intel/compiler: Add Gen11+ native float type
2018-02-28 11:15:47 -08:00
brw_eu.c
intel/compiler: Mark line, pln, and lrp as removed on Gen11+
2018-02-28 11:15:47 -08:00
brw_eu.h
intel/eu: Plumb header present bit to codegen helpers for HDC messages.
2018-03-02 11:28:56 -08:00
brw_fs_bank_conflicts.cpp
intel/fs/bank_conflicts: Use posix_memalign() instead of overaligned new to obtain vector storage.
2017-12-21 15:19:59 -08:00
brw_fs_builder.h
intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.
2018-03-02 11:28:56 -08:00
brw_fs_cmod_propagation.cpp
intel/compiler: Don't propagate cmod into integer multiplies
2017-10-05 11:54:49 -07:00
brw_fs_combine_constants.cpp
…
brw_fs_copy_propagation.cpp
intel/fs: Optimize and simplify the copy propagation dataflow logic.
2018-01-17 11:56:08 -08:00
brw_fs_cse.cpp
…
brw_fs_dead_code_eliminate.cpp
…
brw_fs_generator.cpp
intel/eu: Plumb header present bit to codegen helpers for HDC messages.
2018-03-02 11:28:56 -08:00
brw_fs_live_variables.cpp
intel/fs: Restrict live intervals to the subset possibly reachable from any definition.
2017-12-07 18:27:04 -08:00
brw_fs_live_variables.h
intel/fs: Restrict live intervals to the subset possibly reachable from any definition.
2017-12-07 18:27:04 -08:00
brw_fs_lower_conversions.cpp
i965/fs: rename lower_d2x to lower_conversions
2017-04-14 14:56:07 -07:00
brw_fs_lower_pack.cpp
…
brw_fs_nir.cpp
Revert "i965/fs: Predicate byte scattered writes if needed"
2018-03-02 11:28:56 -08:00
brw_fs_reg_allocate.cpp
intel/fs: Take into account amount of data read in spilling cost heuristic.
2017-04-24 11:01:40 -07:00
brw_fs_register_coalesce.cpp
…
brw_fs_saturate_propagation.cpp
i965/fs: Handle negating immediates on MADs when propagating saturates
2017-11-21 10:13:07 -08:00
brw_fs_sel_peephole.cpp
i965/fs: Do not move MOVs writing the flag outside of control flow
2017-07-20 16:56:49 -07:00
brw_fs_surface_builder.cpp
i965/fs: Add byte scattered read message and fs support
2017-12-06 08:57:18 +01:00
brw_fs_surface_builder.h
i965/fs: Add byte scattered read message and fs support
2017-12-06 08:57:18 +01:00
brw_fs_validate.cpp
…
brw_fs_visitor.cpp
intel/fs: Initialize fs_visitor::grf_used on construction.
2017-12-21 15:20:17 -08:00
brw_fs.cpp
intel/fs: Handle surface opcode sample masks via predication.
2018-03-02 11:28:56 -08:00
brw_fs.h
i965/fs: shuffle_32bit_load_result_to_16bit_data now skips components
2018-02-28 21:37:40 -08:00
brw_inst.h
i965: Add align1 ternary instruction-word support
2017-10-20 15:00:17 -07:00
brw_interpolation_map.c
…
brw_ir_allocator.h
…
brw_ir_fs.h
i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type
2017-12-06 08:57:18 +01:00
brw_ir_vec4.h
i965/vec4: don't do horizontal stride on some register file types
2017-04-14 14:56:09 -07:00
brw_nir_analyze_boolean_resolves.c
…
brw_nir_analyze_ubo_ranges.c
intel/compiler: fix 64bit value prints on 32bit
2018-02-10 17:59:02 +02:00
brw_nir_attribute_workarounds.c
i965: Drop support for the legacy SNORM -> Float equation.
2018-01-02 16:51:42 -08:00
brw_nir_lower_cs_intrinsics.c
intel/cs: Push subgroup ID instead of base thread ID
2017-11-07 10:37:52 -08:00
brw_nir_opt_peephole_ffma.c
…
brw_nir_tcs_workarounds.c
nir: Get rid of nir_shader::stage
2017-10-20 12:49:17 -07:00
brw_nir_trig_workarounds.py
intel: use a flag instead of setting PYTHONPATH
2017-09-27 09:07:28 -07:00
brw_nir.c
i965: remove unused brw_nir_lower_cs_shared()
2018-02-07 08:38:01 +11:00
brw_nir.h
i965: remove unused brw_nir_lower_cs_shared()
2018-02-07 08:38:01 +11:00
brw_packed_float.c
…
brw_predicated_break.cpp
…
brw_reg_type.c
intel/compiler: Add Gen11+ native float type
2018-02-28 11:15:47 -08:00
brw_reg_type.h
intel/compiler: Add Gen11+ native float type
2018-02-28 11:15:47 -08:00
brw_reg.h
intel/ir: Allow representing additional flag subregisters in the IR.
2018-03-02 11:28:56 -08:00
brw_schedule_instructions.cpp
intel/ir: Allow representing additional flag subregisters in the IR.
2018-03-02 11:28:56 -08:00
brw_shader.cpp
intel/compiler: Add Gen11+ native float type
2018-02-28 11:15:47 -08:00
brw_shader.h
intel/ir: Allow representing additional flag subregisters in the IR.
2018-03-02 11:28:56 -08:00
brw_vec4_builder.h
intel/compiler: Lower flrp32 on Gen11+
2018-02-28 11:15:47 -08:00
brw_vec4_cmod_propagation.cpp
intel/compiler: Don't propagate cmod into integer multiplies
2017-10-05 11:54:49 -07:00
brw_vec4_copy_propagation.cpp
i965: Support copy propagating of untyped atomic surface indexes.
2017-09-26 15:35:14 -07:00
brw_vec4_cse.cpp
…
brw_vec4_dead_code_eliminate.cpp
i965/vec4/dce: improve track of partial flag register writes
2017-04-14 14:56:09 -07:00
brw_vec4_generator.cpp
intel/eu: Plumb header present bit to codegen helpers for HDC messages.
2018-03-02 11:28:56 -08:00
brw_vec4_gs_nir.cpp
i965/vec4: Delete the system value infastructure
2017-05-09 15:08:07 -07:00
brw_vec4_gs_visitor.cpp
intel/compiler: Remove final_program_size from brw_compile_*
2017-10-31 23:36:54 -07:00
brw_vec4_gs_visitor.h
i965/vec4: Delete the system value infastructure
2017-05-09 15:08:07 -07:00
brw_vec4_live_variables.cpp
…
brw_vec4_live_variables.h
i965/vec4: consider subregister offset in live variables
2017-04-14 14:56:08 -07:00
brw_vec4_nir.cpp
i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.
2017-12-30 20:30:34 -08:00
brw_vec4_reg_allocate.cpp
i965/vec4: Return float from spill_cost_for_type()
2017-08-21 14:45:44 -07:00
brw_vec4_surface_builder.cpp
i965/vec4: Fix swizzles on atomic sources.
2017-09-26 15:35:11 -07:00
brw_vec4_surface_builder.h
…
brw_vec4_tcs.cpp
intel/compiler: Remove final_program_size from brw_compile_*
2017-10-31 23:36:54 -07:00
brw_vec4_tcs.h
i965/vec4: Delete the system value infastructure
2017-05-09 15:08:07 -07:00
brw_vec4_tes.cpp
i965/vec4: Delete the system value infastructure
2017-05-09 15:08:07 -07:00
brw_vec4_tes.h
i965/vec4: Delete the system value infastructure
2017-05-09 15:08:07 -07:00
brw_vec4_visitor.cpp
intel/compiler: Lower flrp32 on Gen11+
2018-02-28 11:15:47 -08:00
brw_vec4_vs_visitor.cpp
i965: Drop support for the legacy SNORM -> Float equation.
2018-01-02 16:51:42 -08:00
brw_vec4_vs.h
i965: Drop support for the legacy SNORM -> Float equation.
2018-01-02 16:51:42 -08:00
brw_vec4.cpp
intel/ir: Allow representing additional flag subregisters in the IR.
2018-03-02 11:28:56 -08:00
brw_vec4.h
intel/compiler: Move the destructor from vec4_visitor to backend_shader
2017-11-07 10:37:52 -08:00
brw_vue_map.c
…
brw_wm_iz.cpp
nir: Embed the shader_info in the nir_shader again
2017-05-09 15:07:47 -07:00
gen6_gs_visitor.cpp
i965: Move SOL PSIZ hacks from draw time to link time.
2017-06-01 00:08:29 -07:00
gen6_gs_visitor.h
…
meson.build
meson: Use dependencies for nir
2018-01-11 15:40:02 -08:00
test_eu_compact.cpp
intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.
2018-02-27 11:42:39 -08:00
test_eu_validate.cpp
intel/compiler: Add ICL to test_eu_validate.cpp
2018-02-28 11:15:47 -08:00
test_fs_cmod_propagation.cpp
…
test_fs_copy_propagation.cpp
…
test_fs_saturate_propagation.cpp
i965/fs: Check ADD/MAD with immediates in satprop unit test
2017-11-21 10:13:07 -08:00
test_vec4_cmod_propagation.cpp
…
test_vec4_copy_propagation.cpp
…
test_vec4_register_coalesce.cpp
…
test_vf_float_conversions.cpp
…