45e935800a
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31075>
671 lines
22 KiB
Python
671 lines
22 KiB
Python
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template = """\
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/*
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* Copyright (c) 2019 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*
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* This file was generated by aco_builder_h.py
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*/
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#ifndef _ACO_BUILDER_
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#define _ACO_BUILDER_
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#include "aco_ir.h"
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namespace aco {
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enum dpp_ctrl {
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_dpp_quad_perm = 0x000,
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_dpp_row_sl = 0x100,
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_dpp_row_sr = 0x110,
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_dpp_row_rr = 0x120,
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dpp_wf_sl1 = 0x130,
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dpp_wf_rl1 = 0x134,
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dpp_wf_sr1 = 0x138,
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dpp_wf_rr1 = 0x13C,
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dpp_row_mirror = 0x140,
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dpp_row_half_mirror = 0x141,
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dpp_row_bcast15 = 0x142,
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dpp_row_bcast31 = 0x143,
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_dpp_row_share = 0x150,
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_dpp_row_xmask = 0x160,
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};
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inline dpp_ctrl
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dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
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{
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assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
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return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
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}
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inline dpp_ctrl
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dpp_row_sl(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
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}
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inline dpp_ctrl
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dpp_row_sr(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
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}
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inline dpp_ctrl
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dpp_row_rr(unsigned amount)
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{
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assert(amount > 0 && amount < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount);
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}
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inline dpp_ctrl
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dpp_row_share(unsigned lane)
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{
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assert(lane < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_share) | lane);
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}
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inline dpp_ctrl
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dpp_row_xmask(unsigned mask)
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{
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assert(mask < 16);
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return (dpp_ctrl)(((unsigned) _dpp_row_xmask) | mask);
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}
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inline unsigned
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ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
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{
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assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
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return and_mask | (or_mask << 5) | (xor_mask << 10);
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}
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inline unsigned
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ds_pattern_rotate(unsigned delta, unsigned mask)
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{
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assert(delta < 32 && mask < 32);
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return mask | (delta << 5) | 0xc000;
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}
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aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
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enum sendmsg {
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sendmsg_none = 0,
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sendmsg_gs = 2, /* gfx6 to gfx10.3 */
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sendmsg_gs_done = 3, /* gfx6 to gfx10.3 */
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sendmsg_hs_tessfactor = 2, /* gfx11+ */
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sendmsg_dealloc_vgprs = 3, /* gfx11+ */
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sendmsg_save_wave = 4, /* gfx8 to gfx10.3 */
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sendmsg_stall_wave_gen = 5, /* gfx9+ */
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sendmsg_halt_waves = 6, /* gfx9+ */
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sendmsg_ordered_ps_done = 7, /* gfx9+ */
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sendmsg_early_prim_dealloc = 8, /* gfx9 to gfx10 */
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sendmsg_gs_alloc_req = 9, /* gfx9+ */
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sendmsg_get_doorbell = 10, /* gfx9 to gfx10.3 */
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sendmsg_get_ddid = 11, /* gfx10 to gfx10.3 */
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sendmsg_id_mask = 0xf,
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};
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/* gfx11+ */
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enum sendmsg_rtn {
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sendmsg_rtn_get_doorbell = 0,
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sendmsg_rtn_get_ddid = 1,
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sendmsg_rtn_get_tma = 2,
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sendmsg_rtn_get_realtime = 3,
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sendmsg_rtn_save_wave = 4,
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sendmsg_rtn_get_tba = 5,
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sendmsg_rtn_mask = 0xff,
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};
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enum bperm_swiz {
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bperm_b1_sign = 8,
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bperm_b3_sign = 9,
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bperm_b5_sign = 10,
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bperm_b7_sign = 11,
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bperm_0 = 12,
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bperm_255 = 13,
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};
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enum class alu_delay_wait {
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NO_DEP = 0,
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VALU_DEP_1 = 1,
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VALU_DEP_2 = 2,
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VALU_DEP_3 = 3,
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VALU_DEP_4 = 4,
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TRANS32_DEP_1 = 5,
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TRANS32_DEP_2 = 6,
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TRANS32_DEP_3 = 7,
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FMA_ACCUM_CYCLE_1 = 8,
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SALU_CYCLE_1 = 9,
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SALU_CYCLE_2 = 10,
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SALU_CYCLE_3 = 11,
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};
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class Builder {
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public:
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struct Result {
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Instruction *instr;
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Result(Instruction *instr_) : instr(instr_) {}
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operator Instruction *() const {
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return instr;
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}
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operator Temp() const {
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return instr->definitions[0].getTemp();
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}
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operator Operand() const {
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return Operand((Temp)*this);
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}
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Definition& def(unsigned index) const {
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return instr->definitions[index];
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}
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aco_ptr<Instruction> get_ptr() const {
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return aco_ptr<Instruction>(instr);
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}
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Instruction * operator * () const {
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return instr;
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}
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Instruction * operator -> () const {
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return instr;
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}
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};
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struct Op {
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Operand op;
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Op(Temp tmp) : op(tmp) {}
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Op(Operand op_) : op(op_) {}
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Op(Result res) : op((Temp)res) {}
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};
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enum WaveSpecificOpcode {
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s_cselect = (unsigned) aco_opcode::s_cselect_b64,
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s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
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s_and = (unsigned) aco_opcode::s_and_b64,
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s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
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s_or = (unsigned) aco_opcode::s_or_b64,
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s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
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s_not = (unsigned) aco_opcode::s_not_b64,
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s_mov = (unsigned) aco_opcode::s_mov_b64,
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s_wqm = (unsigned) aco_opcode::s_wqm_b64,
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s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
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s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
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s_xnor = (unsigned) aco_opcode::s_xnor_b64,
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s_xor = (unsigned) aco_opcode::s_xor_b64,
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s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
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s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
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s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
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s_flbit_i32 = (unsigned) aco_opcode::s_flbit_i32_b64,
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s_lshl = (unsigned) aco_opcode::s_lshl_b64,
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};
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Program *program;
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bool use_iterator;
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bool start; // only when use_iterator == false
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RegClass lm;
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std::vector<aco_ptr<Instruction>> *instructions;
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std::vector<aco_ptr<Instruction>>::iterator it;
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bool is_precise = false;
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bool is_sz_preserve = false;
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bool is_inf_preserve = false;
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bool is_nan_preserve = false;
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bool is_nuw = false;
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Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(NULL) {}
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Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
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Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
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Builder precise() const {
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Builder res = *this;
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res.is_precise = true;
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return res;
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};
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Builder nuw() const {
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Builder res = *this;
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res.is_nuw = true;
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return res;
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}
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void moveEnd(Block *block) {
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instructions = &block->instructions;
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}
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void reset() {
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use_iterator = false;
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start = false;
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instructions = NULL;
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}
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void reset(Block *block) {
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use_iterator = false;
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start = false;
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instructions = &block->instructions;
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}
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void reset(std::vector<aco_ptr<Instruction>> *instrs) {
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use_iterator = false;
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start = false;
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instructions = instrs;
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}
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void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
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use_iterator = true;
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start = false;
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instructions = instrs;
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it = instr_it;
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}
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Result insert(aco_ptr<Instruction> instr) {
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Instruction *instr_ptr = instr.get();
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if (instructions) {
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if (use_iterator) {
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it = instructions->emplace(it, std::move(instr));
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it = std::next(it);
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} else if (!start) {
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instructions->emplace_back(std::move(instr));
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} else {
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instructions->emplace(instructions->begin(), std::move(instr));
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}
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}
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return Result(instr_ptr);
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}
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Result insert(Instruction* instr) {
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if (instructions) {
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if (use_iterator) {
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it = instructions->emplace(it, aco_ptr<Instruction>(instr));
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it = std::next(it);
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} else if (!start) {
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instructions->emplace_back(aco_ptr<Instruction>(instr));
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} else {
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instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
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}
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}
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return Result(instr);
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}
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Temp tmp(RegClass rc) {
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return program->allocateTmp(rc);
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}
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Temp tmp(RegType type, unsigned size) {
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return tmp(RegClass(type, size));
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}
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Definition def(RegClass rc) {
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return Definition(program->allocateTmp(rc));
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}
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Definition def(RegType type, unsigned size) {
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return def(RegClass(type, size));
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}
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Definition def(RegClass rc, PhysReg reg) {
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return Definition(program->allocateId(rc), reg, rc);
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}
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inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
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if (program->wave_size == 64)
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return (aco_opcode) opcode;
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switch (opcode) {
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case s_cselect:
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return aco_opcode::s_cselect_b32;
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case s_cmp_lg:
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return aco_opcode::s_cmp_lg_u32;
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case s_and:
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return aco_opcode::s_and_b32;
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case s_andn2:
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return aco_opcode::s_andn2_b32;
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case s_or:
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return aco_opcode::s_or_b32;
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case s_orn2:
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return aco_opcode::s_orn2_b32;
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case s_not:
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return aco_opcode::s_not_b32;
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case s_mov:
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return aco_opcode::s_mov_b32;
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case s_wqm:
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return aco_opcode::s_wqm_b32;
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case s_and_saveexec:
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return aco_opcode::s_and_saveexec_b32;
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case s_or_saveexec:
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return aco_opcode::s_or_saveexec_b32;
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case s_xnor:
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return aco_opcode::s_xnor_b32;
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case s_xor:
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return aco_opcode::s_xor_b32;
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case s_bcnt1_i32:
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return aco_opcode::s_bcnt1_i32_b32;
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case s_bitcmp1:
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return aco_opcode::s_bitcmp1_b32;
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case s_ff1_i32:
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return aco_opcode::s_ff1_i32_b32;
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case s_flbit_i32:
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return aco_opcode::s_flbit_i32_b32;
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case s_lshl:
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return aco_opcode::s_lshl_b32;
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default:
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unreachable("Unsupported wave specific opcode.");
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}
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}
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% for fixed in ['m0', 'vcc', 'exec', 'scc']:
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Operand ${fixed}(Temp tmp) {
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% if fixed == 'vcc' or fixed == 'exec':
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//vcc_hi and exec_hi can still be used in wave32
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assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8);
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% endif
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Operand op(tmp);
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op.setFixed(aco::${fixed});
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return op;
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}
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Definition ${fixed}(Definition def) {
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% if fixed == 'vcc' or fixed == 'exec':
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//vcc_hi and exec_hi can still be used in wave32
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assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
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% endif
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def.setFixed(aco::${fixed});
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return def;
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}
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% endfor
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Operand set16bit(Operand op) {
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op.set16bit(true);
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return op;
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}
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Operand set24bit(Operand op) {
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op.set24bit(true);
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return op;
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}
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/* hand-written helpers */
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Temp as_uniform(Op op)
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{
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assert(op.op.isTemp());
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if (op.op.getTemp().type() == RegType::vgpr)
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return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
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else
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return op.op.getTemp();
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}
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Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool tmpu24=false, bool tmpi24=false)
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{
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assert(tmp.type() == RegType::vgpr);
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/* Assume 24bit if high 8 bits of tmp don't impact the result. */
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if ((imm & 0xff) == 0) {
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tmpu24 = true;
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tmpi24 = true;
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}
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tmpu24 &= imm <= 0xffffffu;
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tmpi24 &= imm <= 0x7fffffu || imm >= 0xff800000u;
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bool has_lshl_add = program->gfx_level >= GFX9;
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/* v_mul_lo_u32 has 1.6x the latency of most VALU on GFX10 (8 vs 5 cycles),
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* compared to 4x the latency on <GFX10. */
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unsigned mul_cost = program->gfx_level >= GFX10 ? 1 : (4 + Operand::c32(imm).isLiteral());
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if (imm == 0) {
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return copy(dst, Operand::zero());
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} else if (imm == 1) {
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return copy(dst, Operand(tmp));
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} else if (imm == 0xffffffff) {
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return vsub32(dst, Operand::zero(), tmp);
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} else if (util_is_power_of_two_or_zero(imm)) {
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return vop2(aco_opcode::v_lshlrev_b32, dst, Operand::c32(ffs(imm) - 1u), tmp);
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} else if (tmpu24) {
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return vop2(aco_opcode::v_mul_u32_u24, dst, Operand::c32(imm), tmp);
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} else if (tmpi24) {
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return vop2(aco_opcode::v_mul_i32_i24, dst, Operand::c32(imm), tmp);
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} else if (util_is_power_of_two_nonzero(imm - 1u)) {
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return vadd32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm - 1u) - 1u), tmp), tmp);
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} else if (mul_cost > 2 && util_is_power_of_two_nonzero(imm + 1u)) {
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return vsub32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm + 1u) - 1u), tmp), tmp);
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}
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unsigned instrs_required = util_bitcount(imm);
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if (!has_lshl_add) {
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instrs_required = util_bitcount(imm) - (imm & 0x1); /* shifts */
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instrs_required += util_bitcount(imm) - 1; /* additions */
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}
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if (instrs_required < mul_cost) {
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Result res(NULL);
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Temp cur;
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while (imm) {
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unsigned shift = u_bit_scan(&imm);
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Definition tmp_dst = imm ? def(v1) : dst;
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if (shift && cur.id())
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res = vadd32(Definition(tmp_dst), vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(shift), tmp), cur);
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else if (shift)
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res = vop2(aco_opcode::v_lshlrev_b32, Definition(tmp_dst), Operand::c32(shift), tmp);
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else if (cur.id())
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res = vadd32(Definition(tmp_dst), tmp, cur);
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else
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tmp_dst = Definition(tmp);
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cur = tmp_dst.getTemp();
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}
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return res;
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}
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Temp imm_tmp = copy(def(s1), Operand::c32(imm));
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return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
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}
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Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
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{
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return v_mul_imm(dst, tmp, imm & 0xffffffu, true);
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}
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Result copy(Definition dst, Op op) {
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return pseudo(aco_opcode::p_parallelcopy, dst, op);
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}
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Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
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if (b.op.isConstant() || b.op.regClass().type() != RegType::vgpr)
|
|
std::swap(a, b);
|
|
if (!post_ra && (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr))
|
|
b = copy(def(v1), b);
|
|
|
|
if (!carry_in.op.isUndefined())
|
|
return vop2(aco_opcode::v_addc_co_u32, Definition(dst), def(lm), a, b, carry_in);
|
|
else if (program->gfx_level >= GFX10 && carry_out)
|
|
return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b);
|
|
else if (program->gfx_level < GFX9 || carry_out)
|
|
return vop2(aco_opcode::v_add_co_u32, Definition(dst), def(lm), a, b);
|
|
else
|
|
return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
|
|
}
|
|
|
|
Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
|
|
{
|
|
if (!borrow.op.isUndefined() || program->gfx_level < GFX9)
|
|
carry_out = true;
|
|
|
|
bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
|
|
if (reverse)
|
|
std::swap(a, b);
|
|
if (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr)
|
|
b = copy(def(v1), b);
|
|
|
|
aco_opcode op;
|
|
Temp carry;
|
|
if (carry_out) {
|
|
carry = tmp(lm);
|
|
if (borrow.op.isUndefined())
|
|
op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
|
|
else
|
|
op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
|
|
} else {
|
|
op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
|
|
}
|
|
bool vop3 = false;
|
|
if (program->gfx_level >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
|
|
vop3 = true;
|
|
op = aco_opcode::v_subrev_co_u32_e64;
|
|
} else if (program->gfx_level >= GFX10 && op == aco_opcode::v_sub_co_u32) {
|
|
vop3 = true;
|
|
op = aco_opcode::v_sub_co_u32_e64;
|
|
}
|
|
|
|
int num_ops = borrow.op.isUndefined() ? 2 : 3;
|
|
int num_defs = carry_out ? 2 : 1;
|
|
aco_ptr<Instruction> sub;
|
|
if (vop3)
|
|
sub.reset(create_instruction(op, Format::VOP3, num_ops, num_defs));
|
|
else
|
|
sub.reset(create_instruction(op, Format::VOP2, num_ops, num_defs));
|
|
sub->operands[0] = a.op;
|
|
sub->operands[1] = b.op;
|
|
if (!borrow.op.isUndefined())
|
|
sub->operands[2] = borrow.op;
|
|
sub->definitions[0] = dst;
|
|
if (carry_out)
|
|
sub->definitions[1] = Definition(carry);
|
|
|
|
return insert(std::move(sub));
|
|
}
|
|
|
|
Result readlane(Definition dst, Op vsrc, Op lane)
|
|
{
|
|
if (program->gfx_level >= GFX8)
|
|
return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
|
|
else
|
|
return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
|
|
}
|
|
Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
|
|
if (program->gfx_level >= GFX8)
|
|
return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
|
|
else
|
|
return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
|
|
}
|
|
<%
|
|
import itertools
|
|
formats = [("pseudo", [Format.PSEUDO], list(itertools.product(range(5), range(6))) + [(8, 1), (1, 8), (2, 6), (3, 6), (1, 7)]),
|
|
("sop1", [Format.SOP1], [(0, 1), (1, 0), (1, 1), (2, 1), (3, 2)]),
|
|
("sop2", [Format.SOP2], itertools.product([1, 2], [2, 3])),
|
|
("sopk", [Format.SOPK], itertools.product([0, 1, 2], [0, 1])),
|
|
("sopp", [Format.SOPP], itertools.product([0, 1], [0, 1])),
|
|
("sopc", [Format.SOPC], [(1, 2)]),
|
|
("smem", [Format.SMEM], [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (1, 1), (0, 0)]),
|
|
("ds", [Format.DS], [(1, 0), (1, 1), (1, 2), (1, 3), (0, 3), (0, 4)]),
|
|
("ldsdir", [Format.LDSDIR], [(1, 1)]),
|
|
("mubuf", [Format.MUBUF], [(0, 4), (1, 3), (1, 4)]),
|
|
("mtbuf", [Format.MTBUF], [(0, 4), (1, 3)]),
|
|
("mimg", [Format.MIMG], itertools.product([0, 1], [3, 4, 5, 6, 7])),
|
|
("exp", [Format.EXP], [(0, 4), (0, 5)]),
|
|
("branch", [Format.PSEUDO_BRANCH], itertools.product([1], [0, 1])),
|
|
("barrier", [Format.PSEUDO_BARRIER], [(0, 0)]),
|
|
("reduction", [Format.PSEUDO_REDUCTION], [(3, 3)]),
|
|
("vop1", [Format.VOP1], [(0, 0), (1, 1), (2, 2)]),
|
|
("vop1_sdwa", [Format.VOP1, Format.SDWA], [(1, 1)]),
|
|
("vop2", [Format.VOP2], itertools.product([1, 2], [2, 3])),
|
|
("vop2_sdwa", [Format.VOP2, Format.SDWA], itertools.product([1, 2], [2, 3])),
|
|
("vopc", [Format.VOPC], itertools.product([1, 2], [2])),
|
|
("vopc_sdwa", [Format.VOPC, Format.SDWA], itertools.product([1, 2], [2])),
|
|
("vop3", [Format.VOP3], [(1, 3), (1, 2), (1, 1), (2, 2)]),
|
|
("vop3p", [Format.VOP3P], [(1, 2), (1, 3)]),
|
|
("vopd", [Format.VOPD], [(2, 2), (2, 3), (2, 4), (2, 5), (2, 6)]),
|
|
("vinterp_inreg", [Format.VINTERP_INREG], [(1, 3)]),
|
|
("vintrp", [Format.VINTRP], [(1, 2), (1, 3)]),
|
|
("vop1_dpp", [Format.VOP1, Format.DPP16], [(1, 1)]),
|
|
("vop2_dpp", [Format.VOP2, Format.DPP16], itertools.product([1, 2], [2, 3])),
|
|
("vopc_dpp", [Format.VOPC, Format.DPP16], itertools.product([1, 2], [2])),
|
|
("vop3_dpp", [Format.VOP3, Format.DPP16], [(1, 3), (1, 2), (1, 1), (2, 2)]),
|
|
("vop3p_dpp", [Format.VOP3P, Format.DPP16], [(1, 2), (1, 3)]),
|
|
("vop1_dpp8", [Format.VOP1, Format.DPP8], [(1, 1)]),
|
|
("vop2_dpp8", [Format.VOP2, Format.DPP8], itertools.product([1, 2], [2, 3])),
|
|
("vopc_dpp8", [Format.VOPC, Format.DPP8], itertools.product([1, 2], [2])),
|
|
("vop3_dpp8", [Format.VOP3, Format.DPP8], [(1, 3), (1, 2), (1, 1), (2, 2)]),
|
|
("vop3p_dpp8", [Format.VOP3P, Format.DPP8], [(1, 2), (1, 3)]),
|
|
("vop1_e64", [Format.VOP1, Format.VOP3], itertools.product([1], [1])),
|
|
("vop2_e64", [Format.VOP2, Format.VOP3], itertools.product([1, 2], [2, 3])),
|
|
("vopc_e64", [Format.VOPC, Format.VOP3], itertools.product([1, 2], [2])),
|
|
("vop1_e64_dpp", [Format.VOP1, Format.VOP3, Format.DPP16], itertools.product([1], [1])),
|
|
("vop2_e64_dpp", [Format.VOP2, Format.VOP3, Format.DPP16], itertools.product([1, 2], [2, 3])),
|
|
("vopc_e64_dpp", [Format.VOPC, Format.VOP3, Format.DPP16], itertools.product([1, 2], [2])),
|
|
("vop1_e64_dpp8", [Format.VOP1, Format.VOP3, Format.DPP8], itertools.product([1], [1])),
|
|
("vop2_e64_dpp8", [Format.VOP2, Format.VOP3, Format.DPP8], itertools.product([1, 2], [2, 3])),
|
|
("vopc_e64_dpp8", [Format.VOPC, Format.VOP3, Format.DPP8], itertools.product([1, 2], [2])),
|
|
("flat", [Format.FLAT], [(0, 3), (1, 2), (1, 3)]),
|
|
("global", [Format.GLOBAL], [(0, 3), (1, 2), (1, 3)]),
|
|
("scratch", [Format.SCRATCH], [(0, 3), (1, 2), (1, 3)])]
|
|
formats = [(f if len(f) == 5 else f + ('',)) for f in formats]
|
|
%>\\
|
|
% for name, formats, shapes, extra_field_setup in formats:
|
|
% for num_definitions, num_operands in shapes:
|
|
<%
|
|
args = ['aco_opcode opcode']
|
|
for i in range(num_definitions):
|
|
args.append('Definition def%d' % i)
|
|
for i in range(num_operands):
|
|
args.append('Op op%d' % i)
|
|
for f in formats:
|
|
args += f.get_builder_field_decls()
|
|
%>\\
|
|
|
|
Result ${name}(${', '.join(args)})
|
|
{
|
|
Instruction* instr = create_instruction(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
|
|
% for i in range(num_definitions):
|
|
instr->definitions[${i}] = def${i};
|
|
instr->definitions[${i}].setPrecise(is_precise);
|
|
instr->definitions[${i}].setSZPreserve(is_sz_preserve);
|
|
instr->definitions[${i}].setInfPreserve(is_inf_preserve);
|
|
instr->definitions[${i}].setNaNPreserve(is_nan_preserve);
|
|
instr->definitions[${i}].setNUW(is_nuw);
|
|
% endfor
|
|
% for i in range(num_operands):
|
|
instr->operands[${i}] = op${i}.op;
|
|
% endfor
|
|
% for f in formats:
|
|
% for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
|
|
instr->${f.get_accessor()}().${dest} = ${field_name};
|
|
% endfor
|
|
${f.get_builder_initialization(num_operands)}
|
|
% endfor
|
|
${extra_field_setup}
|
|
return insert(instr);
|
|
}
|
|
|
|
% if name == 'sop1' or name == 'sop2' or name == 'sopc':
|
|
<%
|
|
args[0] = 'WaveSpecificOpcode opcode'
|
|
params = []
|
|
for i in range(num_definitions):
|
|
params.append('def%d' % i)
|
|
for i in range(num_operands):
|
|
params.append('op%d' % i)
|
|
%>\\
|
|
|
|
inline Result ${name}(${', '.join(args)})
|
|
{
|
|
return ${name}(w64or32(opcode), ${', '.join(params)});
|
|
}
|
|
|
|
% endif
|
|
% endfor
|
|
% endfor
|
|
};
|
|
|
|
void hw_init_scratch(Builder& bld, Definition def, Operand scratch_addr, Operand scratch_offset);
|
|
|
|
} // namespace aco
|
|
|
|
#endif /* _ACO_BUILDER_ */"""
|
|
|
|
from aco_opcodes import Format
|
|
from mako.template import Template
|
|
|
|
print(Template(template).render(Format=Format))
|