44e48751d2
This adds some generic infrastructure that allows splitting any instruction into a number of instructions of a smaller legal execution type. This is meant to replace several instances of handcrafted 64bit type lowering done manually in the code generator, which is rather error-prone, prevents scheduling of the lowered instructions, and makes them invisible to the SWSB pass on Gfx12+ platforms, which will become especially problematic on Gfx12.5+ since the EUs introduce multiple asynchronous execution pipelines which the SWSB pass needs to be able to synchronize to one another, so it's critical for the real execution type of the instruction to be visible to the SWSB pass. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
584 lines
21 KiB
C++
584 lines
21 KiB
C++
/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "brw_fs_builder.h"
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using namespace brw;
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namespace {
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/* From the SKL PRM Vol 2a, "Move":
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*
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* "A mov with the same source and destination type, no source modifier,
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* and no saturation is a raw move. A packed byte destination region (B
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* or UB type with HorzStride == 1 and ExecSize > 1) can only be written
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* using raw move."
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*/
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bool
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is_byte_raw_mov(const fs_inst *inst)
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{
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return type_sz(inst->dst.type) == 1 &&
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inst->opcode == BRW_OPCODE_MOV &&
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inst->src[0].type == inst->dst.type &&
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!inst->saturate &&
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!inst->src[0].negate &&
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!inst->src[0].abs;
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}
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/*
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* Return an acceptable byte stride for the destination of an instruction
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* that requires it to have some particular alignment.
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*/
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unsigned
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required_dst_byte_stride(const fs_inst *inst)
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{
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if (inst->dst.is_accumulator()) {
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/* If the destination is an accumulator, insist that we leave the
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* stride alone. We cannot "fix" accumulator destinations by writing
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* to a temporary and emitting a MOV into the original destination.
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* For multiply instructions (our one use of the accumulator), the
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* MUL writes the full 66 bits of the accumulator whereas the MOV we
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* would emit only writes 33 bits and leaves the top 33 bits
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* undefined.
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*
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* It's safe to just require the original stride here because the
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* lowering pass will detect the mismatch in has_invalid_src_region
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* and fix the sources of the multiply instead of the destination.
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*/
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return inst->dst.stride * type_sz(inst->dst.type);
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} else if (type_sz(inst->dst.type) < get_exec_type_size(inst) &&
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!is_byte_raw_mov(inst)) {
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return get_exec_type_size(inst);
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} else {
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/* Calculate the maximum byte stride and the minimum/maximum type
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* size across all source and destination operands we are required to
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* lower.
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*/
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unsigned max_stride = inst->dst.stride * type_sz(inst->dst.type);
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unsigned min_size = type_sz(inst->dst.type);
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unsigned max_size = type_sz(inst->dst.type);
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for (unsigned i = 0; i < inst->sources; i++) {
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if (!is_uniform(inst->src[i]) && !inst->is_control_source(i)) {
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const unsigned size = type_sz(inst->src[i].type);
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max_stride = MAX2(max_stride, inst->src[i].stride * size);
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min_size = MIN2(min_size, size);
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max_size = MAX2(max_size, size);
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}
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}
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/* All operands involved in lowering need to fit in the calculated
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* stride.
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*/
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assert(max_size <= 4 * min_size);
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/* Attempt to use the largest byte stride among all present operands,
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* but never exceed a stride of 4 since that would lead to illegal
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* destination regions during lowering.
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*/
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return MIN2(max_stride, 4 * min_size);
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}
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}
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/*
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* Return an acceptable byte sub-register offset for the destination of an
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* instruction that requires it to be aligned to the sub-register offset of
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* the sources.
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*/
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unsigned
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required_dst_byte_offset(const fs_inst *inst)
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{
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for (unsigned i = 0; i < inst->sources; i++) {
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if (!is_uniform(inst->src[i]) && !inst->is_control_source(i))
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if (reg_offset(inst->src[i]) % REG_SIZE !=
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reg_offset(inst->dst) % REG_SIZE)
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return 0;
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}
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return reg_offset(inst->dst) % REG_SIZE;
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}
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/*
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* Return the closest legal execution type for an instruction on
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* the specified platform.
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*/
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brw_reg_type
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required_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
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{
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const brw_reg_type t = get_exec_type(inst);
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switch (inst->opcode) {
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case SHADER_OPCODE_SHUFFLE:
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case SHADER_OPCODE_QUAD_SWIZZLE:
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if (has_dst_aligned_region_restriction(devinfo, inst))
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return brw_int_type(type_sz(t), false);
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else
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return t;
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case SHADER_OPCODE_BROADCAST:
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case SHADER_OPCODE_MOV_INDIRECT:
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if (((devinfo->verx10 == 70 ||
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devinfo->platform == INTEL_PLATFORM_CHV ||
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intel_device_info_is_9lp(devinfo) ||
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devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
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(devinfo->verx10 >= 125 &&
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brw_reg_type_is_floating_point(inst->src[0].type)))
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return brw_int_type(type_sz(t), false);
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else
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return t;
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default:
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return t;
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}
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}
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/*
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* Return whether the instruction has an unsupported channel bit layout
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* specified for the i-th source region.
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*/
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bool
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has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst,
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unsigned i)
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{
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if (is_unordered(inst) || inst->is_control_source(i))
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return false;
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/* Empirical testing shows that Broadwell has a bug affecting half-float
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* MAD instructions when any of its sources has a non-zero offset, such
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* as:
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*
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* mad(8) g18<1>HF -g17<4,4,1>HF g14.8<4,4,1>HF g11<4,4,1>HF { align16 1Q };
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*
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* We used to generate code like this for SIMD8 executions where we
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* used to pack components Y and W of a vector at offset 16B of a SIMD
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* register. The problem doesn't occur if the stride of the source is 0.
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*/
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if (devinfo->ver == 8 &&
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inst->opcode == BRW_OPCODE_MAD &&
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inst->src[i].type == BRW_REGISTER_TYPE_HF &&
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reg_offset(inst->src[i]) % REG_SIZE > 0 &&
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inst->src[i].stride != 0) {
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return true;
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}
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const unsigned dst_byte_stride = inst->dst.stride * type_sz(inst->dst.type);
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const unsigned src_byte_stride = inst->src[i].stride *
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type_sz(inst->src[i].type);
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const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE;
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const unsigned src_byte_offset = reg_offset(inst->src[i]) % REG_SIZE;
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return has_dst_aligned_region_restriction(devinfo, inst) &&
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!is_uniform(inst->src[i]) &&
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(src_byte_stride != dst_byte_stride ||
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src_byte_offset != dst_byte_offset);
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}
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/*
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* Return whether the instruction has an unsupported channel bit layout
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* specified for the destination region.
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*/
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bool
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has_invalid_dst_region(const intel_device_info *devinfo,
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const fs_inst *inst)
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{
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if (is_unordered(inst)) {
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return false;
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} else {
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const brw_reg_type exec_type = get_exec_type(inst);
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const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE;
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const unsigned dst_byte_stride = inst->dst.stride * type_sz(inst->dst.type);
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const bool is_narrowing_conversion = !is_byte_raw_mov(inst) &&
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type_sz(inst->dst.type) < type_sz(exec_type);
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return (has_dst_aligned_region_restriction(devinfo, inst) &&
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(required_dst_byte_stride(inst) != dst_byte_stride ||
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required_dst_byte_offset(inst) != dst_byte_offset)) ||
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(is_narrowing_conversion &&
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required_dst_byte_stride(inst) != dst_byte_stride);
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}
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}
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/**
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* Return a non-zero value if the execution type of the instruction is
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* unsupported. The destination and sources matching the returned mask
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* will be bit-cast to an integer type of appropriate size, lowering any
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* source or destination modifiers into separate MOV instructions.
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*/
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unsigned
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has_invalid_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
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{
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if (required_exec_type(devinfo, inst) != get_exec_type(inst)) {
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switch (inst->opcode) {
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case SHADER_OPCODE_SHUFFLE:
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case SHADER_OPCODE_QUAD_SWIZZLE:
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case SHADER_OPCODE_BROADCAST:
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case SHADER_OPCODE_MOV_INDIRECT:
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return 0x1;
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default:
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unreachable("Unknown invalid execution type source mask.");
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}
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} else {
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return 0;
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}
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}
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/*
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* Return whether the instruction has unsupported source modifiers
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* specified for the i-th source region.
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*/
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bool
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has_invalid_src_modifiers(const intel_device_info *devinfo,
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const fs_inst *inst, unsigned i)
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{
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return (!inst->can_do_source_mods(devinfo) &&
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(inst->src[i].negate || inst->src[i].abs)) ||
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((has_invalid_exec_type(devinfo, inst) & (1u << i)) &&
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(inst->src[i].negate || inst->src[i].abs ||
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inst->src[i].type != get_exec_type(inst)));
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}
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/*
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* Return whether the instruction has an unsupported type conversion
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* specified for the destination.
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*/
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bool
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has_invalid_conversion(const intel_device_info *devinfo, const fs_inst *inst)
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{
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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return false;
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case BRW_OPCODE_SEL:
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return inst->dst.type != get_exec_type(inst);
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default:
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/* FIXME: We assume the opcodes not explicitly mentioned before just
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* work fine with arbitrary conversions, unless they need to be
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* bit-cast.
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*/
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return has_invalid_exec_type(devinfo, inst) &&
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inst->dst.type != get_exec_type(inst);
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}
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}
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/**
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* Return whether the instruction has unsupported destination modifiers.
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*/
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bool
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has_invalid_dst_modifiers(const intel_device_info *devinfo, const fs_inst *inst)
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{
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return (has_invalid_exec_type(devinfo, inst) &&
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(inst->saturate || inst->conditional_mod)) ||
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has_invalid_conversion(devinfo, inst);
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}
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/**
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* Return whether the instruction has non-standard semantics for the
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* conditional mod which don't cause the flag register to be updated with
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* the comparison result.
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*/
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bool
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has_inconsistent_cmod(const fs_inst *inst)
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{
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return inst->opcode == BRW_OPCODE_SEL ||
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inst->opcode == BRW_OPCODE_CSEL ||
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inst->opcode == BRW_OPCODE_IF ||
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inst->opcode == BRW_OPCODE_WHILE;
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}
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bool
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lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst);
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}
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namespace brw {
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/**
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* Remove any modifiers from the \p i-th source region of the instruction,
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* including negate, abs and any implicit type conversion to the execution
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* type. Instead any source modifiers will be implemented as a separate
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* MOV instruction prior to the original instruction.
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*/
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bool
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lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i)
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{
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assert(inst->components_read(i) == 1);
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assert(v->devinfo->has_integer_dword_mul ||
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inst->opcode != BRW_OPCODE_MUL ||
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brw_reg_type_is_floating_point(get_exec_type(inst)) ||
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MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4 ||
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type_sz(inst->src[i].type) == get_exec_type_size(inst));
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const fs_builder ibld(v, block, inst);
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const fs_reg tmp = ibld.vgrf(get_exec_type(inst));
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lower_instruction(v, block, ibld.MOV(tmp, inst->src[i]));
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inst->src[i] = tmp;
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return true;
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}
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}
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namespace {
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/**
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* Remove any modifiers from the destination region of the instruction,
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* including saturate, conditional mod and any implicit type conversion
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* from the execution type. Instead any destination modifiers will be
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* implemented as a separate MOV instruction after the original
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* instruction.
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*/
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bool
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lower_dst_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst)
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{
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const fs_builder ibld(v, block, inst);
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const brw_reg_type type = get_exec_type(inst);
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/* Not strictly necessary, but if possible use a temporary with the same
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* channel alignment as the current destination in order to avoid
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* violating the restrictions enforced later on by lower_src_region()
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* and lower_dst_region(), which would introduce additional copy
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* instructions into the program unnecessarily.
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*/
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const unsigned stride =
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type_sz(inst->dst.type) * inst->dst.stride <= type_sz(type) ? 1 :
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type_sz(inst->dst.type) * inst->dst.stride / type_sz(type);
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fs_reg tmp = ibld.vgrf(type, stride);
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ibld.UNDEF(tmp);
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tmp = horiz_stride(tmp, stride);
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/* Emit a MOV taking care of all the destination modifiers. */
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fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp);
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mov->saturate = inst->saturate;
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if (!has_inconsistent_cmod(inst))
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mov->conditional_mod = inst->conditional_mod;
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if (inst->opcode != BRW_OPCODE_SEL) {
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mov->predicate = inst->predicate;
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mov->predicate_inverse = inst->predicate_inverse;
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}
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mov->flag_subreg = inst->flag_subreg;
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lower_instruction(v, block, mov);
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/* Point the original instruction at the temporary, and clean up any
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* destination modifiers.
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*/
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assert(inst->size_written == inst->dst.component_size(inst->exec_size));
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inst->dst = tmp;
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inst->size_written = inst->dst.component_size(inst->exec_size);
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inst->saturate = false;
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if (!has_inconsistent_cmod(inst))
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inst->conditional_mod = BRW_CONDITIONAL_NONE;
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assert(!inst->flags_written(v->devinfo) || !mov->predicate);
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return true;
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}
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/**
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* Remove any non-trivial shuffling of data from the \p i-th source region
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* of the instruction. Instead implement the region as a series of integer
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* copies into a temporary with the same channel layout as the destination.
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*/
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bool
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lower_src_region(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i)
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{
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assert(inst->components_read(i) == 1);
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const fs_builder ibld(v, block, inst);
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const unsigned stride = type_sz(inst->dst.type) * inst->dst.stride /
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type_sz(inst->src[i].type);
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assert(stride > 0);
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fs_reg tmp = ibld.vgrf(inst->src[i].type, stride);
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ibld.UNDEF(tmp);
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tmp = horiz_stride(tmp, stride);
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/* Emit a series of 32-bit integer copies with any source modifiers
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* cleaned up (because their semantics are dependent on the type).
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*/
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const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4),
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false);
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const unsigned n = type_sz(tmp.type) / type_sz(raw_type);
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fs_reg raw_src = inst->src[i];
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raw_src.negate = false;
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raw_src.abs = false;
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for (unsigned j = 0; j < n; j++)
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ibld.MOV(subscript(tmp, raw_type, j), subscript(raw_src, raw_type, j));
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/* Point the original instruction at the temporary, making sure to keep
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* any source modifiers in the instruction.
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*/
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fs_reg lower_src = tmp;
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lower_src.negate = inst->src[i].negate;
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lower_src.abs = inst->src[i].abs;
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inst->src[i] = lower_src;
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return true;
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}
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/**
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* Remove any non-trivial shuffling of data from the destination region of
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* the instruction. Instead implement the region as a series of integer
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* copies from a temporary with a channel layout compatible with the
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* sources.
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*/
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bool
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lower_dst_region(fs_visitor *v, bblock_t *block, fs_inst *inst)
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{
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/* We cannot replace the result of an integer multiply which writes the
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* accumulator because MUL+MACH pairs act on the accumulator as a 66-bit
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* value whereas the MOV will act on only 32 or 33 bits of the
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* accumulator.
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*/
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assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() ||
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brw_reg_type_is_floating_point(inst->dst.type));
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const fs_builder ibld(v, block, inst);
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const unsigned stride = required_dst_byte_stride(inst) /
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type_sz(inst->dst.type);
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assert(stride > 0);
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fs_reg tmp = ibld.vgrf(inst->dst.type, stride);
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ibld.UNDEF(tmp);
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tmp = horiz_stride(tmp, stride);
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/* Emit a series of 32-bit integer copies from the temporary into the
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* original destination.
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*/
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const brw_reg_type raw_type = brw_int_type(MIN2(type_sz(tmp.type), 4),
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false);
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const unsigned n = type_sz(tmp.type) / type_sz(raw_type);
|
|
|
|
if (inst->predicate && inst->opcode != BRW_OPCODE_SEL) {
|
|
/* Note that in general we cannot simply predicate the copies on the
|
|
* same flag register as the original instruction, since it may have
|
|
* been overwritten by the instruction itself. Instead initialize
|
|
* the temporary with the previous contents of the destination
|
|
* register.
|
|
*/
|
|
for (unsigned j = 0; j < n; j++)
|
|
ibld.MOV(subscript(tmp, raw_type, j),
|
|
subscript(inst->dst, raw_type, j));
|
|
}
|
|
|
|
for (unsigned j = 0; j < n; j++)
|
|
ibld.at(block, inst->next).MOV(subscript(inst->dst, raw_type, j),
|
|
subscript(tmp, raw_type, j));
|
|
|
|
/* Point the original instruction at the temporary, making sure to keep
|
|
* any destination modifiers in the instruction.
|
|
*/
|
|
assert(inst->size_written == inst->dst.component_size(inst->exec_size));
|
|
inst->dst = tmp;
|
|
inst->size_written = inst->dst.component_size(inst->exec_size);
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* Change sources and destination of the instruction to an
|
|
* appropriate legal type, splitting the instruction into multiple
|
|
* ones of smaller execution type if necessary, to be used in cases
|
|
* where the execution type of an instruction is unsupported.
|
|
*/
|
|
bool
|
|
lower_exec_type(fs_visitor *v, bblock_t *block, fs_inst *inst)
|
|
{
|
|
assert(inst->dst.type == get_exec_type(inst));
|
|
const unsigned mask = has_invalid_exec_type(v->devinfo, inst);
|
|
const brw_reg_type raw_type = required_exec_type(v->devinfo, inst);
|
|
const unsigned n = get_exec_type_size(inst) / type_sz(raw_type);
|
|
const fs_builder ibld(v, block, inst);
|
|
|
|
fs_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride);
|
|
ibld.UNDEF(tmp);
|
|
tmp = horiz_stride(tmp, inst->dst.stride);
|
|
|
|
for (unsigned j = 0; j < n; j++) {
|
|
fs_inst sub_inst = *inst;
|
|
|
|
for (unsigned i = 0; i < inst->sources; i++) {
|
|
if (mask & (1u << i)) {
|
|
assert(inst->src[i].type == inst->dst.type);
|
|
sub_inst.src[i] = subscript(inst->src[i], raw_type, j);
|
|
}
|
|
}
|
|
|
|
sub_inst.dst = subscript(tmp, raw_type, j);
|
|
|
|
assert(sub_inst.size_written == sub_inst.dst.component_size(sub_inst.exec_size));
|
|
assert(!sub_inst.flags_written(v->devinfo) && !sub_inst.saturate);
|
|
ibld.emit(sub_inst);
|
|
|
|
fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j),
|
|
subscript(tmp, raw_type, j));
|
|
if (inst->opcode != BRW_OPCODE_SEL) {
|
|
mov->predicate = inst->predicate;
|
|
mov->predicate_inverse = inst->predicate_inverse;
|
|
}
|
|
lower_instruction(v, block, mov);
|
|
}
|
|
|
|
inst->remove(block);
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* Legalize the source and destination regioning controls of the specified
|
|
* instruction.
|
|
*/
|
|
bool
|
|
lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst)
|
|
{
|
|
const intel_device_info *devinfo = v->devinfo;
|
|
bool progress = false;
|
|
|
|
if (has_invalid_dst_modifiers(devinfo, inst))
|
|
progress |= lower_dst_modifiers(v, block, inst);
|
|
|
|
if (has_invalid_dst_region(devinfo, inst))
|
|
progress |= lower_dst_region(v, block, inst);
|
|
|
|
for (unsigned i = 0; i < inst->sources; i++) {
|
|
if (has_invalid_src_modifiers(devinfo, inst, i))
|
|
progress |= lower_src_modifiers(v, block, inst, i);
|
|
|
|
if (has_invalid_src_region(devinfo, inst, i))
|
|
progress |= lower_src_region(v, block, inst, i);
|
|
}
|
|
|
|
if (has_invalid_exec_type(devinfo, inst))
|
|
progress |= lower_exec_type(v, block, inst);
|
|
|
|
return progress;
|
|
}
|
|
}
|
|
|
|
bool
|
|
fs_visitor::lower_regioning()
|
|
{
|
|
bool progress = false;
|
|
|
|
foreach_block_and_inst_safe(block, fs_inst, inst, cfg)
|
|
progress |= lower_instruction(this, block, inst);
|
|
|
|
if (progress)
|
|
invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
|
|
|
|
return progress;
|
|
}
|