
This function is used in two different scenarios that for 32-bit instructions are the same, but for 16-bit instructions are not. One scenario is that in which we are working at a SIMD8 register level and we need to know if a register is fully defined or written. This is useful, for example, in the context of liveness analysis or register allocation, where we work with units of registers. The other scenario is that in which we want to know if an instruction is writing a full scalar component or just some subset of it. This is useful, for example, in the context of some optimization passes like copy propagation. For 32-bit instructions (or larger), a SIMD8 dispatch will always write at least a full SIMD8 register (32B) if the write is not partial. The function is_partial_write() checks this to determine if we have a partial write. However, when we deal with 16-bit instructions, that logic disables some optimizations that should be safe. For example, a SIMD8 16-bit MOV will only update half of a SIMD register, but it is still a complete write of the variable for a SIMD8 dispatch, so we should not prevent copy propagation in this scenario because we don't write all 32 bytes in the SIMD register or because the write starts at offset 16B (wehere we pack components Y or W of 16-bit vectors). This is a problem for SIMD8 executions (VS, TCS, TES, GS) of 16-bit instructions, which lose a number of optimizations because of this, most important of which is copy-propagation. This patch splits is_partial_write() into is_partial_reg_write(), which represents the current is_partial_write(), useful for things like liveness analysis, and is_partial_var_write(), which considers the dispatch size to check if we are writing a full variable (rather than a full register) to decide if the write is partial or not, which is what we really want in many optimization passes. Then the patch goes on and rewrites all uses of is_partial_write() to use one or the other version. Specifically, we use is_partial_var_write() in the following places: copy propagation, cmod propagation, common subexpression elimination, saturate propagation and sel peephole. Notice that the semantics of is_partial_var_write() exactly match the current implementation of is_partial_write() for anything that is 32-bit or larger, so no changes are expected for 32-bit instructions. Tested against ~5000 tests involving 16-bit instructions in CTS produced the following changes in instruction counts: Patched | Master | % | ================================================ SIMD8 | 621,900 | 706,721 | -12.00% | ================================================ SIMD16 | 93,252 | 93,252 | 0.00% | ================================================ As expected, the change only affects SIMD8 dispatches. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
222 lines
7.0 KiB
C++
222 lines
7.0 KiB
C++
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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/** @file brw_fs_sel_peephole.cpp
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*
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* This file contains the opt_peephole_sel() optimization pass that replaces
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* MOV instructions to the same destination in the "then" and "else" bodies of
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* an if statement with SEL instructions.
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*/
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/* Four MOVs seems to be pretty typical, so I picked the next power of two in
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* the hopes that it would handle almost anything possible in a single
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* pass.
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*/
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#define MAX_MOVS 8 /**< The maximum number of MOVs to attempt to match. */
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using namespace brw;
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/**
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* Scans forwards from an IF counting consecutive MOV instructions in the
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* "then" and "else" blocks of the if statement.
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*
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* A pointer to the bblock_t following the IF is passed as the <then_block>
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* argument. The function stores pointers to the MOV instructions in the
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* <then_mov> and <else_mov> arrays.
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*
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* \return the minimum number of MOVs found in the two branches or zero if
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* an error occurred.
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*
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* E.g.:
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* IF ...
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* then_mov[0] = MOV g4, ...
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* then_mov[1] = MOV g5, ...
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* then_mov[2] = MOV g6, ...
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* ELSE ...
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* else_mov[0] = MOV g4, ...
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* else_mov[1] = MOV g5, ...
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* else_mov[2] = MOV g7, ...
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* ENDIF
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* returns 3.
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*/
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static int
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count_movs_from_if(fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS],
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bblock_t *then_block, bblock_t *else_block)
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{
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int then_movs = 0;
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foreach_inst_in_block(fs_inst, inst, then_block) {
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if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
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inst->flags_written())
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break;
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then_mov[then_movs] = inst;
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then_movs++;
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}
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int else_movs = 0;
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foreach_inst_in_block(fs_inst, inst, else_block) {
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if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||
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inst->flags_written())
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break;
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else_mov[else_movs] = inst;
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else_movs++;
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}
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return MIN2(then_movs, else_movs);
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}
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/**
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* Try to replace IF/MOV+/ELSE/MOV+/ENDIF with SEL.
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*
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* Many GLSL shaders contain the following pattern:
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*
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* x = condition ? foo : bar
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*
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* or
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*
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* if (...) a.xyzw = foo.xyzw;
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* else a.xyzw = bar.xyzw;
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*
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* The compiler emits an ir_if tree for this, since each subexpression might be
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* a complex tree that could have side-effects or short-circuit logic.
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*
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* However, the common case is to simply select one of two constants or
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* variable values---which is exactly what SEL is for. In this case, the
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* assembly looks like:
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*
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* (+f0) IF
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* MOV dst src0
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* ...
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* ELSE
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* MOV dst src1
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* ...
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* ENDIF
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*
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* where each pair of MOVs to a common destination and can be easily translated
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* into
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*
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* (+f0) SEL dst src0 src1
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*
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* If src0 is an immediate value, we promote it to a temporary GRF.
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*/
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bool
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fs_visitor::opt_peephole_sel()
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{
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bool progress = false;
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foreach_block (block, cfg) {
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/* IF instructions, by definition, can only be found at the ends of
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* basic blocks.
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*/
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fs_inst *if_inst = (fs_inst *)block->end();
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if (if_inst->opcode != BRW_OPCODE_IF)
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continue;
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fs_inst *else_mov[MAX_MOVS] = { NULL };
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fs_inst *then_mov[MAX_MOVS] = { NULL };
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bblock_t *then_block = block->next();
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bblock_t *else_block = NULL;
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foreach_list_typed(bblock_link, child, link, &block->children) {
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if (child->block != then_block) {
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if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) {
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else_block = child->block;
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}
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break;
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}
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}
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if (else_block == NULL)
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continue;
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int movs = count_movs_from_if(then_mov, else_mov, then_block, else_block);
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if (movs == 0)
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continue;
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/* Generate SEL instructions for pairs of MOVs to a common destination. */
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for (int i = 0; i < movs; i++) {
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if (!then_mov[i] || !else_mov[i])
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break;
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/* Check that the MOVs are the right form. */
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if (!then_mov[i]->dst.equals(else_mov[i]->dst) ||
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then_mov[i]->exec_size != else_mov[i]->exec_size ||
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then_mov[i]->group != else_mov[i]->group ||
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then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all ||
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then_mov[i]->is_partial_var_write(dispatch_width) ||
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else_mov[i]->is_partial_var_write(dispatch_width) ||
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then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE ||
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else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) {
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movs = i;
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break;
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}
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/* Check that source types for mov operations match. */
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if (then_mov[i]->src[0].type != else_mov[i]->src[0].type) {
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movs = i;
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break;
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}
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}
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if (movs == 0)
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continue;
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for (int i = 0; i < movs; i++) {
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const fs_builder ibld = fs_builder(this, then_block, then_mov[i])
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.at(block, if_inst);
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if (then_mov[i]->src[0].equals(else_mov[i]->src[0])) {
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ibld.MOV(then_mov[i]->dst, then_mov[i]->src[0]);
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} else {
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/* Only the last source register can be a constant, so if the MOV
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* in the "then" clause uses a constant, we need to put it in a
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* temporary.
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*/
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fs_reg src0(then_mov[i]->src[0]);
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if (src0.file == IMM) {
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src0 = ibld.vgrf(then_mov[i]->src[0].type);
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ibld.MOV(src0, then_mov[i]->src[0]);
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}
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set_predicate_inv(if_inst->predicate, if_inst->predicate_inverse,
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ibld.SEL(then_mov[i]->dst, src0,
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else_mov[i]->src[0]));
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}
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then_mov[i]->remove(then_block);
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else_mov[i]->remove(else_block);
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}
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progress = true;
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}
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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