
This function is used in two different scenarios that for 32-bit instructions are the same, but for 16-bit instructions are not. One scenario is that in which we are working at a SIMD8 register level and we need to know if a register is fully defined or written. This is useful, for example, in the context of liveness analysis or register allocation, where we work with units of registers. The other scenario is that in which we want to know if an instruction is writing a full scalar component or just some subset of it. This is useful, for example, in the context of some optimization passes like copy propagation. For 32-bit instructions (or larger), a SIMD8 dispatch will always write at least a full SIMD8 register (32B) if the write is not partial. The function is_partial_write() checks this to determine if we have a partial write. However, when we deal with 16-bit instructions, that logic disables some optimizations that should be safe. For example, a SIMD8 16-bit MOV will only update half of a SIMD register, but it is still a complete write of the variable for a SIMD8 dispatch, so we should not prevent copy propagation in this scenario because we don't write all 32 bytes in the SIMD register or because the write starts at offset 16B (wehere we pack components Y or W of 16-bit vectors). This is a problem for SIMD8 executions (VS, TCS, TES, GS) of 16-bit instructions, which lose a number of optimizations because of this, most important of which is copy-propagation. This patch splits is_partial_write() into is_partial_reg_write(), which represents the current is_partial_write(), useful for things like liveness analysis, and is_partial_var_write(), which considers the dispatch size to check if we are writing a full variable (rather than a full register) to decide if the write is partial or not, which is what we really want in many optimization passes. Then the patch goes on and rewrites all uses of is_partial_write() to use one or the other version. Specifically, we use is_partial_var_write() in the following places: copy propagation, cmod propagation, common subexpression elimination, saturate propagation and sel peephole. Notice that the semantics of is_partial_var_write() exactly match the current implementation of is_partial_write() for anything that is 32-bit or larger, so no changes are expected for 32-bit instructions. Tested against ~5000 tests involving 16-bit instructions in CTS produced the following changes in instruction counts: Patched | Master | % | ================================================ SIMD8 | 621,900 | 706,721 | -12.00% | ================================================ SIMD16 | 93,252 | 93,252 | 0.00% | ================================================ As expected, the change only affects SIMD8 dispatches. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
361 lines
11 KiB
C++
361 lines
11 KiB
C++
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "brw_cfg.h"
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#include "brw_fs_live_variables.h"
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using namespace brw;
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#define MAX_INSTRUCTION (1 << 30)
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/** @file brw_fs_live_variables.cpp
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*
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* Support for calculating liveness information about virtual GRFs.
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*
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* This produces a live interval for each whole virtual GRF. We could
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* choose to expose per-component live intervals for VGRFs of size > 1,
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* but we currently do not. It is easier for the consumers of this
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* information to work with whole VGRFs.
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*
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* However, we internally track use/def information at the per-GRF level for
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* greater accuracy. Large VGRFs may be accessed piecemeal over many
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* (possibly non-adjacent) instructions. In this case, examining a single
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* instruction is insufficient to decide whether a whole VGRF is ultimately
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* used or defined. Tracking individual components allows us to easily
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* assemble this information.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 14.1 (p444).
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*/
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void
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fs_live_variables::setup_one_read(struct block_data *bd, fs_inst *inst,
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int ip, const fs_reg ®)
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{
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int var = var_from_reg(reg);
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assert(var < num_vars);
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start[var] = MIN2(start[var], ip);
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end[var] = MAX2(end[var], ip);
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/* The use[] bitset marks when the block makes use of a variable (VGRF
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* channel) without having completely defined that variable within the
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* block.
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*/
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if (!BITSET_TEST(bd->def, var))
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BITSET_SET(bd->use, var);
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}
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void
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fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst,
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int ip, const fs_reg ®)
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{
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int var = var_from_reg(reg);
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assert(var < num_vars);
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start[var] = MIN2(start[var], ip);
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end[var] = MAX2(end[var], ip);
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/* The def[] bitset marks when an initialization in a block completely
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* screens off previous updates of that variable (VGRF channel).
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*/
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if (inst->dst.file == VGRF) {
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if (!inst->is_partial_reg_write() && !BITSET_TEST(bd->use, var))
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BITSET_SET(bd->def, var);
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BITSET_SET(bd->defout, var);
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}
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}
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/**
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* Sets up the use[] and def[] bitsets.
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*
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* The basic-block-level live variable analysis needs to know which
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* variables get used before they're completely defined, and which
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* variables are completely defined before they're used.
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*
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* These are tracked at the per-component level, rather than whole VGRFs.
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*/
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void
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fs_live_variables::setup_def_use()
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{
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int ip = 0;
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foreach_block (block, cfg) {
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assert(ip == block->start_ip);
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if (block->num > 0)
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assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
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struct block_data *bd = &block_data[block->num];
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foreach_inst_in_block(fs_inst, inst, block) {
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/* Set use[] for this instruction */
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for (unsigned int i = 0; i < inst->sources; i++) {
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fs_reg reg = inst->src[i];
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if (reg.file != VGRF)
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continue;
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for (unsigned j = 0; j < regs_read(inst, i); j++) {
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setup_one_read(bd, inst, ip, reg);
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reg.offset += REG_SIZE;
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}
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}
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bd->flag_use[0] |= inst->flags_read(v->devinfo) & ~bd->flag_def[0];
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/* Set def[] for this instruction */
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if (inst->dst.file == VGRF) {
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fs_reg reg = inst->dst;
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for (unsigned j = 0; j < regs_written(inst); j++) {
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setup_one_write(bd, inst, ip, reg);
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reg.offset += REG_SIZE;
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}
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}
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if (!inst->predicate && inst->exec_size >= 8)
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bd->flag_def[0] |= inst->flags_written() & ~bd->flag_use[0];
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ip++;
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}
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}
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}
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/**
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* The algorithm incrementally sets bits in liveout and livein,
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* propagating it through control flow. It will eventually terminate
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* because it only ever adds bits, and stops when no bits are added in
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* a pass.
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*/
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void
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fs_live_variables::compute_live_variables()
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{
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bool cont = true;
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while (cont) {
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cont = false;
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foreach_block_reverse (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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/* Update liveout */
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foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_liveout = (child_bd->livein[i] &
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~bd->liveout[i]);
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if (new_liveout) {
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bd->liveout[i] |= new_liveout;
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cont = true;
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}
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}
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BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
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~bd->flag_liveout[0]);
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if (new_liveout) {
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bd->flag_liveout[0] |= new_liveout;
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cont = true;
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}
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}
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/* Update livein */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_livein = (bd->use[i] |
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(bd->liveout[i] &
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~bd->def[i]));
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if (new_livein & ~bd->livein[i]) {
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bd->livein[i] |= new_livein;
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cont = true;
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}
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}
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BITSET_WORD new_livein = (bd->flag_use[0] |
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(bd->flag_liveout[0] &
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~bd->flag_def[0]));
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if (new_livein & ~bd->flag_livein[0]) {
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bd->flag_livein[0] |= new_livein;
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cont = true;
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}
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}
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}
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/* Propagate defin and defout down the CFG to calculate the union of live
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* variables potentially defined along any possible control flow path.
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*/
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do {
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cont = false;
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foreach_block (block, cfg) {
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const struct block_data *bd = &block_data[block->num];
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foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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const BITSET_WORD new_def = bd->defout[i] & ~child_bd->defin[i];
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child_bd->defin[i] |= new_def;
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child_bd->defout[i] |= new_def;
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cont |= new_def;
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}
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}
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}
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} while (cont);
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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void
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fs_live_variables::compute_start_end()
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{
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foreach_block (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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for (int i = 0; i < num_vars; i++) {
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if (BITSET_TEST(bd->livein, i) && BITSET_TEST(bd->defin, i)) {
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start[i] = MIN2(start[i], block->start_ip);
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end[i] = MAX2(end[i], block->start_ip);
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}
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if (BITSET_TEST(bd->liveout, i) && BITSET_TEST(bd->defout, i)) {
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start[i] = MIN2(start[i], block->end_ip);
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end[i] = MAX2(end[i], block->end_ip);
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}
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}
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}
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}
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fs_live_variables::fs_live_variables(fs_visitor *v, const cfg_t *cfg)
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: v(v), cfg(cfg)
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{
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mem_ctx = ralloc_context(NULL);
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num_vgrfs = v->alloc.count;
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num_vars = 0;
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var_from_vgrf = rzalloc_array(mem_ctx, int, num_vgrfs);
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for (int i = 0; i < num_vgrfs; i++) {
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var_from_vgrf[i] = num_vars;
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num_vars += v->alloc.sizes[i];
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}
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vgrf_from_var = rzalloc_array(mem_ctx, int, num_vars);
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for (int i = 0; i < num_vgrfs; i++) {
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for (unsigned j = 0; j < v->alloc.sizes[i]; j++) {
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vgrf_from_var[var_from_vgrf[i] + j] = i;
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}
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}
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start = ralloc_array(mem_ctx, int, num_vars);
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end = rzalloc_array(mem_ctx, int, num_vars);
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for (int i = 0; i < num_vars; i++) {
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start[i] = MAX_INSTRUCTION;
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end[i] = -1;
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}
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block_data= rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
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bitset_words = BITSET_WORDS(num_vars);
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for (int i = 0; i < cfg->num_blocks; i++) {
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block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].defin = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].defout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
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block_data[i].flag_def[0] = 0;
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block_data[i].flag_use[0] = 0;
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block_data[i].flag_livein[0] = 0;
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block_data[i].flag_liveout[0] = 0;
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}
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setup_def_use();
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compute_live_variables();
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compute_start_end();
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}
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fs_live_variables::~fs_live_variables()
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{
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ralloc_free(mem_ctx);
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}
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void
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fs_visitor::invalidate_live_intervals()
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{
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ralloc_free(live_intervals);
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live_intervals = NULL;
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}
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/**
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* Compute the live intervals for each virtual GRF.
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*
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* This uses the per-component use/def data, but combines it to produce
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* information about whole VGRFs.
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*/
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void
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fs_visitor::calculate_live_intervals()
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{
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if (this->live_intervals)
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return;
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int num_vgrfs = this->alloc.count;
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ralloc_free(this->virtual_grf_start);
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ralloc_free(this->virtual_grf_end);
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virtual_grf_start = ralloc_array(mem_ctx, int, num_vgrfs);
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virtual_grf_end = ralloc_array(mem_ctx, int, num_vgrfs);
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for (int i = 0; i < num_vgrfs; i++) {
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virtual_grf_start[i] = MAX_INSTRUCTION;
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virtual_grf_end[i] = -1;
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}
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this->live_intervals = new(mem_ctx) fs_live_variables(this, cfg);
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/* Merge the per-component live ranges to whole VGRF live ranges. */
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for (int i = 0; i < live_intervals->num_vars; i++) {
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int vgrf = live_intervals->vgrf_from_var[i];
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virtual_grf_start[vgrf] = MIN2(virtual_grf_start[vgrf],
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live_intervals->start[i]);
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virtual_grf_end[vgrf] = MAX2(virtual_grf_end[vgrf],
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live_intervals->end[i]);
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}
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}
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bool
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fs_live_variables::vars_interfere(int a, int b)
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{
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return !(end[b] <= start[a] ||
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end[a] <= start[b]);
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}
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bool
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fs_visitor::virtual_grf_interferes(int a, int b)
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{
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return !(virtual_grf_end[a] <= virtual_grf_start[b] ||
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virtual_grf_end[b] <= virtual_grf_start[a]);
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}
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