574 lines
25 KiB
C
574 lines
25 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "genX_pipeline_util.h"
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static void
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emit_ia_state(struct anv_pipeline *pipeline,
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const VkPipelineInputAssemblyStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
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.PrimitiveTopologyType = pipeline->topology);
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}
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static void
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emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterizationStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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uint32_t samples = 1;
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if (ms_info)
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samples = ms_info->rasterizationSamples;
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.ViewportTransformEnable = !(extra && extra->disable_viewport),
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 0,
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.PointWidthSource = pipeline->writes_point_size ? Vertex : State,
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.PointWidth = 1.0,
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};
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/* FINISHME: VkBool32 rasterizerDiscardEnable; */
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GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
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struct GENX(3DSTATE_RASTER) raster = {
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GENX(3DSTATE_RASTER_header),
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/* For details on 3DSTATE_RASTER multisample state, see the BSpec table
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* "Multisample Modes State".
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*/
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.DXMultisampleRasterizationEnable = samples > 1,
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.ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
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.ForceMultisampling = false,
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.FrontWinding = vk_to_gen_front_face[info->frontFace],
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.CullMode = vk_to_gen_cullmode[info->cullMode],
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.FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
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.ScissorRectangleEnable = !(extra && extra->disable_scissor),
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#if GEN_GEN == 8
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.ViewportZClipTestEnable = true,
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#else
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/* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
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.ViewportZFarClipTestEnable = true,
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.ViewportZNearClipTestEnable = true,
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#endif
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};
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GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
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}
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static void
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emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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struct anv_device *device = pipeline->device;
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uint32_t num_dwords = GENX(BLEND_STATE_length);
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GENX(BLEND_STATE) blend_state = {
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.AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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};
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for (uint32_t i = 0; i < info->attachmentCount; i++) {
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const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
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if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
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a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
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a->colorBlendOp != a->alphaBlendOp) {
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blend_state.IndependentAlphaBlendEnable = true;
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}
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blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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.ColorBufferBlendEnable = a->blendEnable,
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.PreBlendSourceOnlyClampEnable = false,
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.ColorClampRange = COLORCLAMP_RTFORMAT,
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.PreBlendColorClampEnable = true,
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.PostBlendColorClampEnable = true,
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.SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
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.DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
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.ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
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.AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
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.WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
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.WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
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.WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
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.WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
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};
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/* Our hardware applies the blend factor prior to the blend function
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* regardless of what function is used. Technically, this means the
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* hardware can do MORE than GL or Vulkan specify. However, it also
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* means that, for MIN and MAX, we have to stomp the blend factor to
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* ONE to make it a no-op.
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*/
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if (a->colorBlendOp == VK_BLEND_OP_MIN ||
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a->colorBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
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}
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if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
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a->alphaBlendOp == VK_BLEND_OP_MAX) {
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blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
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blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
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}
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}
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for (uint32_t i = info->attachmentCount; i < 8; i++) {
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blend_state.Entry[i].WriteDisableAlpha = true;
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blend_state.Entry[i].WriteDisableRed = true;
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blend_state.Entry[i].WriteDisableGreen = true;
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blend_state.Entry[i].WriteDisableBlue = true;
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}
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GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
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if (!device->info.has_llc)
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anv_state_clflush(pipeline->blend_state);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
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.BlendStatePointer = pipeline->blend_state.offset,
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.BlendStatePointerValid = true);
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}
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static void
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emit_ds_state(struct anv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *info)
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{
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uint32_t *dw = GEN_GEN == 8 ?
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pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
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if (info == NULL) {
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/* We're going to OR this together with the dynamic state. We need
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* to make sure it's initialized to something useful.
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*/
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memset(pipeline->gen8.wm_depth_stencil, 0,
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sizeof(pipeline->gen8.wm_depth_stencil));
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memset(pipeline->gen9.wm_depth_stencil, 0,
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sizeof(pipeline->gen9.wm_depth_stencil));
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return;
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}
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/* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
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struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
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.DepthTestEnable = info->depthTestEnable,
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.DepthBufferWriteEnable = info->depthWriteEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DoubleSidedStencilEnable = true,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
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.StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
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.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
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.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
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.BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
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.BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
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};
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GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
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}
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static void
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emit_ms_state(struct anv_pipeline *pipeline,
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const VkPipelineMultisampleStateCreateInfo *info)
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{
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uint32_t samples = 1;
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uint32_t log2_samples = 0;
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/* From the Vulkan 1.0 spec:
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* If pSampleMask is NULL, it is treated as if the mask has all bits
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* enabled, i.e. no coverage is removed from fragments.
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*
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* 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
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*/
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uint32_t sample_mask = 0xffff;
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if (info) {
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samples = info->rasterizationSamples;
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log2_samples = __builtin_ffs(samples) - 1;
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}
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if (info && info->pSampleMask)
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sample_mask &= info->pSampleMask[0];
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if (info && info->sampleShadingEnable)
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anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
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/* The PRM says that this bit is valid only for DX9:
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*
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* SW can choose to set this bit only for DX9 API. DX10/OGL API's
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* should not have any effect by setting or not setting this bit.
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*/
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.PixelPositionOffsetEnable = false,
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.PixelLocation = CENTER,
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.NumberofMultisamples = log2_samples);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
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.SampleMask = sample_mask);
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}
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VkResult
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genX(graphics_pipeline_create)(
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VkDevice _device,
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struct anv_pipeline_cache * cache,
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const VkGraphicsPipelineCreateInfo* pCreateInfo,
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const struct anv_graphics_pipeline_create_info *extra,
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const VkAllocationCallbacks* pAllocator,
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_pipeline *pipeline;
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VkResult result;
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uint32_t offset, length;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
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pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (pipeline == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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result = anv_pipeline_init(pipeline, device, cache,
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pCreateInfo, extra, pAllocator);
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if (result != VK_SUCCESS) {
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anv_free2(&device->alloc, pAllocator, pipeline);
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return result;
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}
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assert(pCreateInfo->pVertexInputState);
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emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
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assert(pCreateInfo->pInputAssemblyState);
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emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
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assert(pCreateInfo->pRasterizationState);
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emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
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pCreateInfo->pMultisampleState, extra);
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emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
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emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
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pCreateInfo->pMultisampleState);
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emit_urb_setup(pipeline);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
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.ClipEnable = true,
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.ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
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.MinimumPointWidth = 0.125,
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.MaximumPointWidth = 255.875,
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.MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
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.StatisticsEnable = true,
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.LineEndCapAntialiasingRegionWidth = _05pixels,
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.LineAntialiasingRegionWidth = _10pixels,
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.EarlyDepthStencilControl = NORMAL,
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.ForceThreadDispatchEnable = NORMAL,
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.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
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.BarycentricInterpolationMode =
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pipeline->ps_ksp0 == NO_KERNEL ?
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0 : pipeline->wm_prog_data.barycentric_interp_modes);
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const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
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offset = 1;
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length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
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if (pipeline->gs_kernel == NO_KERNEL)
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
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else
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
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.SingleProgramFlow = false,
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.KernelStartPointer = pipeline->gs_kernel,
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.VectorMaskEnable = false,
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.SamplerCount = 0,
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.BindingTableEntryCount = 0,
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.ExpectedVertexCount = gs_prog_data->vertices_in,
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.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
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.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
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.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
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.OutputTopology = gs_prog_data->output_topology,
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.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
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.IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
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.DispatchGRFStartRegisterForURBData =
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gs_prog_data->base.base.dispatch_grf_start_reg,
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.MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
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.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
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.DispatchMode = gs_prog_data->base.dispatch_mode,
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.StatisticsEnable = true,
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.IncludePrimitiveID = gs_prog_data->include_primitive_id,
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.ReorderMode = TRAILING,
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.Enable = true,
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.ControlDataFormat = gs_prog_data->control_data_format,
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.StaticOutput = gs_prog_data->static_vertex_count >= 0,
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.StaticOutputVertexCount =
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gs_prog_data->static_vertex_count >= 0 ?
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gs_prog_data->static_vertex_count : 0,
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/* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
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* UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
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* UserClipDistanceCullTestEnableBitmask(v)
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*/
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.VertexURBEntryOutputReadOffset = offset,
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.VertexURBEntryOutputLength = length);
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const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
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/* Skip the VUE header and position slots */
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offset = 1;
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length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
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uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
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pipeline->vs_vec4;
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if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
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.FunctionEnable = false,
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/* Even if VS is disabled, SBE still gets the amount of
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* vertex data to read from this field. */
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.VertexURBEntryOutputReadOffset = offset,
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.VertexURBEntryOutputLength = length);
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else
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
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.KernelStartPointer = vs_start,
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.SingleVertexDispatch = false,
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.VectorMaskEnable = false,
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.SamplerCount = 0,
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.BindingTableEntryCount =
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vue_prog_data->base.binding_table.size_bytes / 4,
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.ThreadDispatchPriority = false,
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.FloatingPointMode = IEEE754,
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.IllegalOpcodeExceptionEnable = false,
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.AccessesUAV = false,
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.SoftwareExceptionEnable = false,
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.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
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.PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
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.DispatchGRFStartRegisterForURBData =
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vue_prog_data->base.dispatch_grf_start_reg,
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.VertexURBEntryReadLength = vue_prog_data->urb_read_length,
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.VertexURBEntryReadOffset = 0,
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.MaximumNumberofThreads = device->info.max_vs_threads - 1,
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.StatisticsEnable = false,
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.SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
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.VertexCacheDisable = false,
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.FunctionEnable = true,
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.VertexURBEntryOutputReadOffset = offset,
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.VertexURBEntryOutputLength = length,
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.UserClipDistanceClipTestEnableBitmask = 0,
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.UserClipDistanceCullTestEnableBitmask = 0);
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const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
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const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
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if (pipeline->ps_ksp0 == NO_KERNEL) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
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.PixelShaderValid = false);
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} else {
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/* TODO: We should clean this up. Among other things, this is mostly
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* shared with other gens.
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*/
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const struct brw_vue_map *fs_input_map;
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if (pipeline->gs_kernel == NO_KERNEL)
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fs_input_map = &vue_prog_data->vue_map;
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else
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fs_input_map = &gs_prog_data->base.vue_map;
|
|
|
|
struct GENX(3DSTATE_SBE_SWIZ) swiz = {
|
|
GENX(3DSTATE_SBE_SWIZ_header),
|
|
};
|
|
|
|
int max_source_attr = 0;
|
|
for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
|
|
int input_index = wm_prog_data->urb_setup[attr];
|
|
|
|
if (input_index < 0)
|
|
continue;
|
|
|
|
int source_attr = fs_input_map->varying_to_slot[attr];
|
|
max_source_attr = MAX2(max_source_attr, source_attr);
|
|
|
|
if (input_index >= 16)
|
|
continue;
|
|
|
|
if (source_attr == -1) {
|
|
/* This attribute does not exist in the VUE--that means that the
|
|
* vertex shader did not write to it. It could be that it's a
|
|
* regular varying read by the fragment shader but not written by
|
|
* the vertex shader or it's gl_PrimitiveID. In the first case the
|
|
* value is undefined, in the second it needs to be
|
|
* gl_PrimitiveID.
|
|
*/
|
|
swiz.Attribute[input_index].ConstantSource = PRIM_ID;
|
|
swiz.Attribute[input_index].ComponentOverrideX = true;
|
|
swiz.Attribute[input_index].ComponentOverrideY = true;
|
|
swiz.Attribute[input_index].ComponentOverrideZ = true;
|
|
swiz.Attribute[input_index].ComponentOverrideW = true;
|
|
} else {
|
|
/* We have to subtract two slots to accout for the URB entry output
|
|
* read offset in the VS and GS stages.
|
|
*/
|
|
swiz.Attribute[input_index].SourceAttribute = source_attr - 2;
|
|
}
|
|
}
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
|
|
.AttributeSwizzleEnable = true,
|
|
.ForceVertexURBEntryReadLength = false,
|
|
.ForceVertexURBEntryReadOffset = false,
|
|
.VertexURBEntryReadLength =
|
|
DIV_ROUND_UP(max_source_attr + 1, 2),
|
|
.PointSpriteTextureCoordinateOrigin = UPPERLEFT,
|
|
.NumberofSFOutputAttributes =
|
|
wm_prog_data->num_varying_inputs,
|
|
|
|
#if GEN_GEN >= 9
|
|
.Attribute0ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute1ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute2ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute3ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute4ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute5ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute6ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute7ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute8ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute9ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute10ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute11ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute12ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute13ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute14ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute15ActiveComponentFormat = ACF_XYZW,
|
|
/* wow, much field, very attribute */
|
|
.Attribute16ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute17ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute18ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute19ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute20ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute21ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute22ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute23ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute24ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute25ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute26ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute27ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute28ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute29ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute28ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute29ActiveComponentFormat = ACF_XYZW,
|
|
.Attribute30ActiveComponentFormat = ACF_XYZW,
|
|
#endif
|
|
);
|
|
|
|
uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
|
|
GENX(3DSTATE_SBE_SWIZ_length));
|
|
GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
|
|
.KernelStartPointer0 = pipeline->ps_ksp0,
|
|
|
|
.SingleProgramFlow = false,
|
|
.VectorMaskEnable = true,
|
|
.SamplerCount = 1,
|
|
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
|
|
.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
|
|
|
|
.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
|
|
.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
|
|
POSOFFSET_SAMPLE: POSOFFSET_NONE,
|
|
.PushConstantEnable = wm_prog_data->base.nr_params > 0,
|
|
._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
|
|
._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
|
|
._32PixelDispatchEnable = false,
|
|
|
|
.DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
|
|
.DispatchGRFStartRegisterForConstantSetupData1 = 0,
|
|
.DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
|
|
|
|
.KernelStartPointer1 = 0,
|
|
.KernelStartPointer2 = pipeline->ps_ksp2);
|
|
|
|
bool per_sample_ps = pCreateInfo->pMultisampleState &&
|
|
pCreateInfo->pMultisampleState->sampleShadingEnable;
|
|
|
|
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
|
|
.PixelShaderValid = true,
|
|
.PixelShaderKillsPixel = wm_prog_data->uses_kill,
|
|
.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
|
|
.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
|
|
.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
|
|
.PixelShaderIsPerSample = per_sample_ps,
|
|
.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth,
|
|
.PixelShaderUsesSourceW = wm_prog_data->uses_src_w,
|
|
#if GEN_GEN >= 9
|
|
.PixelShaderPullsBary = wm_prog_data->pulls_bary,
|
|
.InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
|
|
ICMS_INNER_CONSERVATIVE : ICMS_NONE,
|
|
#else
|
|
.PixelShaderUsesInputCoverageMask =
|
|
wm_prog_data->uses_sample_mask,
|
|
#endif
|
|
);
|
|
}
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|