234 lines
8.6 KiB
C
234 lines
8.6 KiB
C
/*
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* Copyright 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "isl_gen8.h"
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#include "isl_priv.h"
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bool
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gen8_choose_msaa_layout(const struct isl_device *dev,
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const struct isl_surf_init_info *info,
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enum isl_tiling tiling,
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enum isl_msaa_layout *msaa_layout)
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{
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bool require_array = false;
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bool require_interleaved = false;
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assert(info->samples >= 1);
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if (info->samples == 1) {
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*msaa_layout = ISL_MSAA_LAYOUT_NONE;
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return true;
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}
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/* From the Broadwell PRM >> Volume2d: Command Structures >>
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* RENDER_SURFACE_STATE Tile Mode:
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*
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* - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
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* must be YMAJOR.
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*
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* As usual, though, stencil is special.
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*/
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if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage))
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return false;
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/* From the Broadwell PRM >> Volume2d: Command Structures >>
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* RENDER_SURFACE_STATE Multisampled Surface Storage Format:
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*
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* All multisampled render target surfaces must have this field set to
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* MSFMT_MSS
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*/
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if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
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require_array = true;
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/* From the Broadwell PRM >> Volume2d: Command Structures >>
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* RENDER_SURFACE_STATE Number of Multisamples:
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*
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* - If this field is any value other than MULTISAMPLECOUNT_1, the
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* Surface Type must be SURFTYPE_2D This field must be set to
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* MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
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* or Render Target surface.
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*
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* - If this field is any value other than MULTISAMPLECOUNT_1, Surface
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* Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
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*/
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if (info->dim != ISL_SURF_DIM_2D)
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return false;
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if (info->levels > 1)
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return false;
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/* More obvious restrictions */
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if (isl_surf_usage_is_display(info->usage))
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return false;
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if (isl_format_is_compressed(info->format))
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return false;
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if (isl_format_is_yuv(info->format))
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return false;
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if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
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(info->usage & ISL_SURF_USAGE_HIZ_BIT))
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require_interleaved = true;
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if (require_array && require_interleaved)
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return false;
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if (require_interleaved) {
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*msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
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return true;
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}
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*msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
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return true;
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}
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/**
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* Choose horizontal subimage alignment, in units of surface elements.
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*/
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static uint32_t
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gen8_choose_halign_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info)
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{
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if (isl_format_is_compressed(info->format))
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return 1;
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/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
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* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
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*
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* - This field is intended to be set to HALIGN_8 only if the surface
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* was rendered as a depth buffer with Z16 format or a stencil buffer.
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* In this case it must be set to HALIGN_8 since these surfaces
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* support only alignment of 8. [...]
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*/
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if (isl_surf_info_is_z16(info))
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return 8;
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if (isl_surf_usage_is_stencil(info->usage))
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return 8;
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/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
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* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
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*
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* [...] For Z32 formats it must be set to HALIGN_4.
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*/
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if (isl_surf_usage_is_depth(info->usage))
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return 4;
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if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
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/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
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* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
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*
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* - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
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* HALIGN 16 must be used.
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*
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* This case handles color surfaces that may own an auxiliary MCS, CCS_D,
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* or CCS_E. Depth buffers, including those that own an auxiliary HiZ
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* surface, are handled above and do not require HALIGN_16.
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*/
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assert(!isl_surf_usage_is_depth(info->usage));
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return 16;
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}
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/* XXX(chadv): I believe the hardware requires each image to be
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* cache-aligned. If that's true, then defaulting to halign=4 is wrong for
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* many formats. Depending on the format's block size, we may need to
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* increase halign to 8.
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*/
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return 4;
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}
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/**
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* Choose vertical subimage alignment, in units of surface elements.
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*/
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static uint32_t
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gen8_choose_valign_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info)
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{
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/* From the Broadwell PRM > Volume 2d: Command Reference: Structures
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* > RENDER_SURFACE_STATE Surface Vertical Alignment (p325):
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*
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* - For Sampling Engine and Render Target Surfaces: This field
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* specifies the vertical alignment requirement in elements for the
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* surface. [...] An element is defined as a pixel in uncompresed
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* surface formats, and as a compression block in compressed surface
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* formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
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* element is a sample.
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*
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* - This field is intended to be set to VALIGN_4 if the surface was
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* rendered as a depth buffer, for a multisampled (4x) render target,
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* or for a multisampled (8x) render target, since these surfaces
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* support only alignment of 4. Use of VALIGN_4 for other surfaces is
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* supported, but increases memory usage.
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*
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* - This field is intended to be set to VALIGN_8 only if the surface
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* was rendered as a stencil buffer, since stencil buffer surfaces
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* support only alignment of 8. If set to VALIGN_8, Surface Format
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* must be R8_UINT.
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*/
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if (isl_format_is_compressed(info->format))
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return 1;
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if (isl_surf_usage_is_stencil(info->usage))
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return 8;
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return 4;
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}
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void
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gen8_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el)
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{
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/* Handled by isl_choose_image_alignment_el */
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assert(info->format != ISL_FORMAT_HIZ);
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assert(!isl_tiling_is_std_y(tiling));
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/* The below text from the Broadwell PRM provides some insight into the
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* hardware's requirements for LOD alignment. From the Broadwell PRM >>
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* Volume 5: Memory Views >> Surface Layout >> 2D Surfaces:
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*
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* These [2D surfaces] must adhere to the following memory organization
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* rules:
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*
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* - For non-compressed texture formats, each mipmap must start on an
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* even row within the monolithic rectangular area. For
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* 1-texel-high mipmaps, this may require a row of padding below
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* the previous mipmap. This restriction does not apply to any
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* compressed texture formats; each subsequent (lower-res)
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* compressed mipmap is positioned directly below the previous
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* mipmap.
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*
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* - Vertical alignment restrictions vary with memory tiling type:
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* 1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled
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* mipmaps are not required to start at the left edge of a tile
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* row.)
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*/
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*image_align_el = (struct isl_extent3d) {
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.w = gen8_choose_halign_el(dev, info),
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.h = gen8_choose_valign_el(dev, info),
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.d = 1,
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};
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}
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