30d7bebc8a
This avoids flushing batches just because e.g. both are reading the same dynamic state streaming buffer, or shader assembly buffer.
565 lines
17 KiB
C
565 lines
17 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* @file iris_batch.c
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*
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* Batchbuffer and command submission module.
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*
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* Every API draw call results in a number of GPU commands, which we
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* collect into a "batch buffer". Typically, many draw calls are grouped
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* into a single batch to amortize command submission overhead.
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*
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* We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
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* One critical piece of data is the "validation list", which contains a
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* list of the buffer objects (BOs) which the commands in the GPU need.
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* The kernel will make sure these are resident and pinned at the correct
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* virtual memory address before executing our batch. If a BO is not in
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* the validation list, it effectively does not exist, so take care.
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*/
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#include "iris_batch.h"
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#include "iris_bufmgr.h"
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#include "iris_context.h"
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#include "drm-uapi/i915_drm.h"
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#include "util/hash_table.h"
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#include "util/set.h"
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#include "main/macros.h"
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#include <errno.h>
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#include <xf86drm.h>
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#define FILE_DEBUG_FLAG DEBUG_BUFMGR
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/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
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* or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
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* need an extra 4 bytes to pad out to the nearest QWord. So reserve 16.
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*/
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#define BATCH_RESERVED 16
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static void
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iris_batch_reset(struct iris_batch *batch);
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/**
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* Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
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*/
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static void
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dump_validation_list(struct iris_batch *batch)
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{
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fprintf(stderr, "Validation list (length %d):\n", batch->exec_count);
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for (int i = 0; i < batch->exec_count; i++) {
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uint64_t flags = batch->validation_list[i].flags;
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assert(batch->validation_list[i].handle ==
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batch->exec_bos[i]->gem_handle);
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fprintf(stderr, "[%2d]: %2d %-14s %p %-7s @ 0x%016llx (%"PRIu64"B) - %d refs\n",
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i,
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batch->validation_list[i].handle,
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batch->exec_bos[i]->name,
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batch->exec_bos[i],
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(flags & EXEC_OBJECT_WRITE) ? "(write)" : "",
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batch->validation_list[i].offset,
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batch->exec_bos[i]->size,
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batch->exec_bos[i]->refcount);
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}
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}
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/**
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* Return BO information to the batch decoder (for debugging).
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*/
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static struct gen_batch_decode_bo
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decode_get_bo(void *v_batch, uint64_t address)
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{
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struct iris_batch *batch = v_batch;
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for (int i = 0; i < batch->exec_count; i++) {
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struct iris_bo *bo = batch->exec_bos[i];
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/* The decoder zeroes out the top 16 bits, so we need to as well */
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uint64_t bo_address = bo->gtt_offset & (~0ull >> 16);
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if (address >= bo_address && address < bo_address + bo->size) {
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return (struct gen_batch_decode_bo) {
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.addr = address,
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.size = bo->size,
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.map = iris_bo_map(batch->dbg, bo, MAP_READ) +
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(address - bo_address),
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};
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}
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}
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return (struct gen_batch_decode_bo) { };
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}
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/**
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* Decode the current batch.
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*/
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static void
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decode_batch(struct iris_batch *batch)
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{
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void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
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gen_print_batch(&batch->decoder, map, batch->primary_batch_size,
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batch->exec_bos[0]->gtt_offset);
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}
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static bool
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uint_key_compare(const void *a, const void *b)
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{
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return a == b;
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}
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static uint32_t
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uint_key_hash(const void *key)
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{
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return (uintptr_t) key;
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}
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void
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iris_init_batch(struct iris_batch *batch,
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struct iris_screen *screen,
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struct iris_vtable *vtbl,
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struct pipe_debug_callback *dbg,
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struct iris_batch **all_batches,
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const char *name,
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uint8_t engine)
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{
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batch->screen = screen;
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batch->vtbl = vtbl;
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batch->dbg = dbg;
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batch->name = name;
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/* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
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assert((engine & ~I915_EXEC_RING_MASK) == 0);
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assert(util_bitcount(engine) == 1);
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batch->engine = engine;
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batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
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assert(batch->hw_ctx_id);
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batch->exec_count = 0;
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batch->exec_array_size = 100;
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batch->exec_bos =
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malloc(batch->exec_array_size * sizeof(batch->exec_bos[0]));
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batch->validation_list =
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malloc(batch->exec_array_size * sizeof(batch->validation_list[0]));
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batch->cache.render = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
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_mesa_key_pointer_equal);
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batch->cache.depth = _mesa_set_create(NULL, _mesa_hash_pointer,
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_mesa_key_pointer_equal);
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memset(batch->other_batches, 0, sizeof(batch->other_batches));
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for (int i = 0, j = 0; i < IRIS_BATCH_COUNT; i++) {
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if (all_batches[i] != batch)
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batch->other_batches[j++] = all_batches[i];
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}
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if (unlikely(INTEL_DEBUG)) {
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batch->state_sizes =
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_mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);
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const unsigned decode_flags =
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GEN_BATCH_DECODE_FULL |
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((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
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GEN_BATCH_DECODE_OFFSETS |
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GEN_BATCH_DECODE_FLOATS;
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gen_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
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stderr, decode_flags, NULL,
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decode_get_bo, NULL, batch);
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batch->decoder.max_vbo_decoded_lines = 32;
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}
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iris_batch_reset(batch);
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}
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#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
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static struct drm_i915_gem_exec_object2 *
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find_validation_entry(struct iris_batch *batch, struct iris_bo *bo)
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{
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unsigned index = READ_ONCE(bo->index);
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if (index < batch->exec_count && batch->exec_bos[index] == bo)
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return &batch->validation_list[index];
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/* May have been shared between multiple active batches */
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for (index = 0; index < batch->exec_count; index++) {
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if (batch->exec_bos[index] == bo)
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return &batch->validation_list[index];
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}
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return NULL;
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}
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/**
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* Add a buffer to the current batch's validation list.
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*
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* You must call this on any BO you wish to use in this batch, to ensure
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* that it's resident when the GPU commands execute.
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*/
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void
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iris_use_pinned_bo(struct iris_batch *batch,
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struct iris_bo *bo,
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bool writable)
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{
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assert(bo->kflags & EXEC_OBJECT_PINNED);
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struct drm_i915_gem_exec_object2 *existing_entry =
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find_validation_entry(batch, bo);
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if (existing_entry) {
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/* The BO is already in the validation list; mark it writable */
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if (writable)
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existing_entry->flags |= EXEC_OBJECT_WRITE;
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return;
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}
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/* This is the first time our batch has seen this BO. Before we use it,
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* we may need to flush and synchronize with other batches.
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*/
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for (int b = 0; b < ARRAY_SIZE(batch->other_batches); b++) {
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struct drm_i915_gem_exec_object2 *other_entry =
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find_validation_entry(batch->other_batches[b], bo);
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/* If the buffer is referenced by another batch, and either batch
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* intends to write it, then flush the other batch and synchronize.
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*
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* Consider these cases:
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*
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* 1. They read, we read => No synchronization required.
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* 2. They read, we write => Synchronize (they need the old value)
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* 3. They write, we read => Synchronize (we need their new value)
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* 4. They write, we write => Synchronize (order writes)
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*
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* The read/read case is very common, as multiple batches usually
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* share a streaming state buffer or shader assembly buffer, and
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* we want to avoid synchronizing in this case.
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*/
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if (other_entry &&
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((other_entry->flags & EXEC_OBJECT_WRITE) || writable)) {
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iris_batch_flush(batch->other_batches[b]);
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}
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}
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/* Now, take a reference and add it to the validation list. */
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iris_bo_reference(bo);
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if (batch->exec_count == batch->exec_array_size) {
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batch->exec_array_size *= 2;
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batch->exec_bos =
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realloc(batch->exec_bos,
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batch->exec_array_size * sizeof(batch->exec_bos[0]));
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batch->validation_list =
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realloc(batch->validation_list,
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batch->exec_array_size * sizeof(batch->validation_list[0]));
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}
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batch->validation_list[batch->exec_count] =
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(struct drm_i915_gem_exec_object2) {
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.handle = bo->gem_handle,
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.offset = bo->gtt_offset,
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.flags = bo->kflags | (writable ? EXEC_OBJECT_WRITE : 0),
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};
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bo->index = batch->exec_count;
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batch->exec_bos[batch->exec_count] = bo;
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batch->aperture_space += bo->size;
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batch->exec_count++;
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}
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static void
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create_batch(struct iris_batch *batch)
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{
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struct iris_screen *screen = batch->screen;
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struct iris_bufmgr *bufmgr = screen->bufmgr;
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batch->bo = iris_bo_alloc(bufmgr, "command buffer",
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BATCH_SZ + BATCH_RESERVED, IRIS_MEMZONE_OTHER);
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batch->bo->kflags |= EXEC_OBJECT_CAPTURE;
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batch->map = iris_bo_map(NULL, batch->bo, MAP_READ | MAP_WRITE);
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batch->map_next = batch->map;
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iris_use_pinned_bo(batch, batch->bo, false);
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}
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static void
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iris_batch_reset(struct iris_batch *batch)
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{
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if (batch->last_bo != NULL) {
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iris_bo_unreference(batch->last_bo);
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batch->last_bo = NULL;
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}
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batch->last_bo = batch->bo;
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batch->primary_batch_size = 0;
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batch->contains_draw = false;
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create_batch(batch);
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assert(batch->bo->index == 0);
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if (batch->state_sizes)
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_mesa_hash_table_clear(batch->state_sizes, NULL);
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iris_cache_sets_clear(batch);
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}
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void
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iris_batch_free(struct iris_batch *batch)
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{
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struct iris_screen *screen = batch->screen;
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struct iris_bufmgr *bufmgr = screen->bufmgr;
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for (int i = 0; i < batch->exec_count; i++) {
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iris_bo_unreference(batch->exec_bos[i]);
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}
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free(batch->exec_bos);
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free(batch->validation_list);
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iris_bo_unreference(batch->bo);
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batch->bo = NULL;
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batch->map = NULL;
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batch->map_next = NULL;
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iris_bo_unreference(batch->last_bo);
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iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
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_mesa_hash_table_destroy(batch->cache.render, NULL);
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_mesa_set_destroy(batch->cache.depth, NULL);
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if (batch->state_sizes) {
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_mesa_hash_table_destroy(batch->state_sizes, NULL);
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gen_batch_decode_ctx_finish(&batch->decoder);
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}
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}
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/**
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* If we've chained to a secondary batch, or are getting near to the end,
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* then flush. This should only be called between draws.
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*/
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void
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iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate)
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{
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if (batch->bo != batch->exec_bos[0] ||
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iris_batch_bytes_used(batch) + estimate >= BATCH_SZ) {
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iris_batch_flush(batch);
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}
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}
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void
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iris_chain_to_new_batch(struct iris_batch *batch)
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{
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/* We only support chaining a single time. */
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assert(batch->bo == batch->exec_bos[0]);
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uint32_t *cmd = batch->map_next;
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uint64_t *addr = batch->map_next + 4;
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batch->map_next += 8;
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/* No longer held by batch->bo, still held by validation list */
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iris_bo_unreference(batch->bo);
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batch->primary_batch_size = iris_batch_bytes_used(batch);
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create_batch(batch);
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/* Emit MI_BATCH_BUFFER_START to chain to another batch. */
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*cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
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*addr = batch->bo->gtt_offset;
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}
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/**
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* Terminate a batch with MI_BATCH_BUFFER_END.
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*/
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static void
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iris_finish_batch(struct iris_batch *batch)
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{
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// XXX: ISP DIS
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/* Emit MI_BATCH_BUFFER_END to finish our batch. */
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uint32_t *map = batch->map_next;
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map[0] = (0xA << 23);
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batch->map_next += 4;
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if (batch->bo == batch->exec_bos[0])
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batch->primary_batch_size = iris_batch_bytes_used(batch);
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}
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/**
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* Submit the batch to the GPU via execbuffer2.
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*/
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static int
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submit_batch(struct iris_batch *batch, int in_fence_fd, int *out_fence_fd)
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{
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iris_bo_unmap(batch->bo);
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/* The requirement for using I915_EXEC_NO_RELOC are:
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*
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* The addresses written in the objects must match the corresponding
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* reloc.gtt_offset which in turn must match the corresponding
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* execobject.offset.
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*
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* Any render targets written to in the batch must be flagged with
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* EXEC_OBJECT_WRITE.
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*
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* To avoid stalling, execobject.offset should match the current
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* address of that object within the active context.
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*/
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struct drm_i915_gem_execbuffer2 execbuf = {
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.buffers_ptr = (uintptr_t) batch->validation_list,
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.buffer_count = batch->exec_count,
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.batch_start_offset = 0,
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/* This must be QWord aligned. */
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.batch_len = ALIGN(batch->primary_batch_size, 8),
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.flags = batch->engine |
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I915_EXEC_NO_RELOC |
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I915_EXEC_BATCH_FIRST |
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I915_EXEC_HANDLE_LUT,
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.rsvd1 = batch->hw_ctx_id, /* rsvd1 is actually the context ID */
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};
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unsigned long cmd = DRM_IOCTL_I915_GEM_EXECBUFFER2;
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if (in_fence_fd != -1) {
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execbuf.rsvd2 = in_fence_fd;
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execbuf.flags |= I915_EXEC_FENCE_IN;
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}
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if (out_fence_fd != NULL) {
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cmd = DRM_IOCTL_I915_GEM_EXECBUFFER2_WR;
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*out_fence_fd = -1;
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execbuf.flags |= I915_EXEC_FENCE_OUT;
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}
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int ret = drm_ioctl(batch->screen->fd, cmd, &execbuf);
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if (ret != 0) {
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ret = -errno;
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DBG("execbuf FAILED: errno = %d\n", -ret);
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fprintf(stderr, "execbuf FAILED: errno = %d\n", -ret);
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abort();
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} else {
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DBG("execbuf succeeded\n");
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}
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for (int i = 0; i < batch->exec_count; i++) {
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struct iris_bo *bo = batch->exec_bos[i];
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bo->idle = false;
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bo->index = -1;
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}
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if (ret == 0 && out_fence_fd != NULL)
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*out_fence_fd = execbuf.rsvd2 >> 32;
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return ret;
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}
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/**
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* Flush the batch buffer, submitting it to the GPU and resetting it so
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* we're ready to emit the next batch.
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*
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* \param in_fence_fd is ignored if -1. Otherwise, this function takes
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* ownership of the fd.
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*
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* \param out_fence_fd is ignored if NULL. Otherwise, the caller must
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* take ownership of the returned fd.
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*/
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int
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_iris_batch_flush_fence(struct iris_batch *batch,
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int in_fence_fd, int *out_fence_fd,
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const char *file, int line)
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{
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if (iris_batch_bytes_used(batch) == 0)
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return 0;
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iris_finish_batch(batch);
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if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
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int bytes_for_commands = iris_batch_bytes_used(batch);
|
|
int second_bytes = 0;
|
|
if (batch->bo != batch->exec_bos[0]) {
|
|
second_bytes = bytes_for_commands;
|
|
bytes_for_commands += batch->primary_batch_size;
|
|
}
|
|
fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) "
|
|
"(cmds), %4d BOs (%0.1fMb aperture)\n",
|
|
file, line, batch->name, batch->hw_ctx_id,
|
|
batch->primary_batch_size, second_bytes,
|
|
100.0f * bytes_for_commands / BATCH_SZ,
|
|
batch->exec_count,
|
|
(float) batch->aperture_space / (1024 * 1024));
|
|
dump_validation_list(batch);
|
|
}
|
|
|
|
if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
|
|
decode_batch(batch);
|
|
}
|
|
|
|
int ret = submit_batch(batch, in_fence_fd, out_fence_fd);
|
|
|
|
//throttle(iris);
|
|
|
|
if (ret >= 0) {
|
|
//if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
|
|
//iris_check_for_reset(ice);
|
|
|
|
if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
|
|
dbg_printf("waiting for idle\n");
|
|
iris_bo_wait_rendering(batch->bo);
|
|
}
|
|
} else {
|
|
#ifdef DEBUG
|
|
const bool color = INTEL_DEBUG & DEBUG_COLOR;
|
|
fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
|
|
color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
|
|
abort();
|
|
#endif
|
|
}
|
|
|
|
/* Clean up after the batch we submitted and prepare for a new one. */
|
|
for (int i = 0; i < batch->exec_count; i++) {
|
|
iris_bo_unreference(batch->exec_bos[i]);
|
|
batch->exec_bos[i] = NULL;
|
|
}
|
|
batch->exec_count = 0;
|
|
batch->aperture_space = 0;
|
|
|
|
/* Start a new batch buffer. */
|
|
iris_batch_reset(batch);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Does the current batch refer to the given BO?
|
|
*
|
|
* (In other words, is the BO in the current batch's validation list?)
|
|
*/
|
|
bool
|
|
iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
|
|
{
|
|
return find_validation_entry(batch, bo) != NULL;
|
|
}
|