Marek Olšák 30af861bff radeonsi: restructure (rewrite) the compute blit shader
This merges the separate MSAA, downsampling, upsampling, and non-MSAA blocks.
It's not meant to change behavior, but some change are necessary:
- disallow 16 samples
- loads only load the number of components that we need
- optimizations barriers are placed optimally and include the sample index
  in the same vector as the coordinates, so that LLVM is forced to form VMEM
  clauses for loads and stores
- the shader queries the descriptor for the dst image manually and passes
  it to the image store instead of the image variable (this is needed to get
  latency hiding for scalar loads in the presence of optimization barriers)

This is a prerequisite for blitting multiple pixels per lane.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28917>
2024-06-08 05:48:11 +00:00
2022-11-22 19:04:13 +00:00
2024-03-13 15:21:07 +00:00
2024-01-24 10:02:10 +00:00
2023-11-02 11:37:46 +00:00
2024-05-13 14:32:12 +00:00
2024-06-01 18:25:28 +00:00
2024-04-24 19:51:59 +00:00

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