2b29342fae
We have to keep it there for the cache to work, so let's not have an extra copy in struct anv_pipeline too.
433 lines
18 KiB
C
433 lines
18 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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static uint32_t
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vertex_element_comp_control(enum isl_format format, unsigned comp)
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{
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uint8_t bits;
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switch (comp) {
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case 0: bits = isl_format_layouts[format].channels.r.bits; break;
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case 1: bits = isl_format_layouts[format].channels.g.bits; break;
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case 2: bits = isl_format_layouts[format].channels.b.bits; break;
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case 3: bits = isl_format_layouts[format].channels.a.bits; break;
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default: unreachable("Invalid component");
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}
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if (bits) {
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return VFCOMP_STORE_SRC;
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} else if (comp < 3) {
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return VFCOMP_STORE_0;
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} else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
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isl_format_layouts[format].channels.r.type == ISL_SINT) {
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assert(comp == 3);
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return VFCOMP_STORE_1_INT;
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} else {
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assert(comp == 3);
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return VFCOMP_STORE_1_FP;
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}
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}
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
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uint32_t elements;
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if (extra && extra->disable_vs) {
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/* If the VS is disabled, just assume the user knows what they're
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* doing and apply the layout blindly. This can only come from
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* meta, so this *should* be safe.
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*/
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elements = 0;
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
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elements |= (1 << info->pVertexAttributeDescriptions[i].location);
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} else {
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/* Pull inputs_read out of the VS prog data */
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uint64_t inputs_read = vs_prog_data->inputs_read;
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assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
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elements = inputs_read >> VERT_ATTRIB_GENERIC0;
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}
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#if GEN_GEN >= 8
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/* On BDW+, we only need to allocate space for base ids. Setting up
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* the actual vertex and instance id is a separate packet.
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*/
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const bool needs_svgs_elem = vs_prog_data->uses_basevertex ||
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vs_prog_data->uses_baseinstance;
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#else
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/* On Haswell and prior, vertex and instance id are created by using the
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* ComponentControl fields, so we need an element for any of them.
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*/
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const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
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vs_prog_data->uses_instanceid ||
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vs_prog_data->uses_basevertex ||
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vs_prog_data->uses_baseinstance;
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#endif
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uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem;
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if (elem_count == 0)
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return;
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uint32_t *p;
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const uint32_t num_dwords = 1 + elem_count * 2;
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p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GENX(3DSTATE_VERTEX_ELEMENTS));
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memset(p + 1, 0, (num_dwords - 1) * 4);
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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enum isl_format format = anv_get_isl_format(desc->format,
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VK_IMAGE_ASPECT_COLOR_BIT,
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VK_IMAGE_TILING_LINEAR,
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NULL);
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assert(desc->binding < 32);
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if ((elements & (1 << desc->location)) == 0)
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continue; /* Binding unused */
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uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
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struct GENX(VERTEX_ELEMENT_STATE) element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offset,
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.Component0Control = vertex_element_comp_control(format, 0),
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.Component1Control = vertex_element_comp_control(format, 1),
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.Component2Control = vertex_element_comp_control(format, 2),
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.Component3Control = vertex_element_comp_control(format, 3),
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};
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GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
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#if GEN_GEN >= 8
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/* On Broadwell and later, we have a separate VF_INSTANCING packet
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* that controls instancing. On Haswell and prior, that's part of
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* VERTEX_BUFFER_STATE which we emit later.
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*/
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
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.InstancingEnable = pipeline->instancing_enable[desc->binding],
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.VertexElementIndex = slot,
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/* Vulkan so far doesn't have an instance divisor, so
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* this is always 1 (ignored if not instancing). */
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.InstanceDataStepRate = 1);
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#endif
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}
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const uint32_t id_slot = __builtin_popcount(elements);
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if (needs_svgs_elem) {
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/* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
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* "Within a VERTEX_ELEMENT_STATE structure, if a Component
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* Control field is set to something other than VFCOMP_STORE_SRC,
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* no higher-numbered Component Control fields may be set to
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* VFCOMP_STORE_SRC"
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*
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* This means, that if we have BaseInstance, we need BaseVertex as
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* well. Just do all or nothing.
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*/
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uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
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vs_prog_data->uses_baseinstance) ?
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VFCOMP_STORE_SRC : VFCOMP_STORE_0;
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struct GENX(VERTEX_ELEMENT_STATE) element = {
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.VertexBufferIndex = 32, /* Reserved for this */
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.Valid = true,
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.SourceElementFormat = ISL_FORMAT_R32G32_UINT,
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.Component0Control = base_ctrl,
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.Component1Control = base_ctrl,
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#if GEN_GEN >= 8
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.Component2Control = VFCOMP_STORE_0,
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.Component3Control = VFCOMP_STORE_0,
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#else
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.Component2Control = VFCOMP_STORE_VID,
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.Component3Control = VFCOMP_STORE_IID,
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#endif
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};
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GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
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}
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#if GEN_GEN >= 8
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
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.VertexIDEnable = vs_prog_data->uses_vertexid,
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.VertexIDComponentNumber = 2,
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.VertexIDElementOffset = id_slot,
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.InstanceIDEnable = vs_prog_data->uses_instanceid,
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.InstanceIDComponentNumber = 3,
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.InstanceIDElementOffset = id_slot);
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#endif
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}
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static inline void
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emit_urb_setup(struct anv_pipeline *pipeline)
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{
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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struct anv_device *device = pipeline->device;
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/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
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*
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* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
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* needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
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* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
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* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
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* needs to be sent before any combination of VS associated 3DSTATE."
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*/
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anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
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.DepthStallEnable = true,
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.PostSyncOperation = WriteImmediateData,
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.Address = { &device->workaround_bo, 0 });
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#endif
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unsigned push_start = 0;
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) {
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unsigned push_size = pipeline->urb.push_size[i];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
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._3DCommandSubOpcode = 18 + i,
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.ConstantBufferOffset = (push_size > 0) ? push_start : 0,
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.ConstantBufferSize = push_size);
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push_start += pipeline->urb.push_size[i];
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}
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for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
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._3DCommandSubOpcode = 48 + i,
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.VSURBStartingAddress = pipeline->urb.start[i],
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.VSURBEntryAllocationSize = pipeline->urb.size[i] - 1,
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.VSNumberofURBEntries = pipeline->urb.entries[i]);
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}
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}
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static void
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emit_3dstate_sbe(struct anv_pipeline *pipeline)
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{
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const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
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const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
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const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
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const struct brw_vue_map *fs_input_map;
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if (pipeline->gs_kernel == NO_KERNEL)
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fs_input_map = &vs_prog_data->base.vue_map;
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else
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fs_input_map = &gs_prog_data->base.vue_map;
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struct GENX(3DSTATE_SBE) sbe = {
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GENX(3DSTATE_SBE_header),
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.AttributeSwizzleEnable = true,
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.PointSpriteTextureCoordinateOrigin = UPPERLEFT,
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.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs,
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#if GEN_GEN >= 9
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.Attribute0ActiveComponentFormat = ACF_XYZW,
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.Attribute1ActiveComponentFormat = ACF_XYZW,
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.Attribute2ActiveComponentFormat = ACF_XYZW,
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.Attribute3ActiveComponentFormat = ACF_XYZW,
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.Attribute4ActiveComponentFormat = ACF_XYZW,
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.Attribute5ActiveComponentFormat = ACF_XYZW,
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.Attribute6ActiveComponentFormat = ACF_XYZW,
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.Attribute7ActiveComponentFormat = ACF_XYZW,
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.Attribute8ActiveComponentFormat = ACF_XYZW,
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.Attribute9ActiveComponentFormat = ACF_XYZW,
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.Attribute10ActiveComponentFormat = ACF_XYZW,
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.Attribute11ActiveComponentFormat = ACF_XYZW,
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.Attribute12ActiveComponentFormat = ACF_XYZW,
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.Attribute13ActiveComponentFormat = ACF_XYZW,
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.Attribute14ActiveComponentFormat = ACF_XYZW,
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.Attribute15ActiveComponentFormat = ACF_XYZW,
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/* wow, much field, very attribute */
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.Attribute16ActiveComponentFormat = ACF_XYZW,
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.Attribute17ActiveComponentFormat = ACF_XYZW,
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.Attribute18ActiveComponentFormat = ACF_XYZW,
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.Attribute19ActiveComponentFormat = ACF_XYZW,
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.Attribute20ActiveComponentFormat = ACF_XYZW,
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.Attribute21ActiveComponentFormat = ACF_XYZW,
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.Attribute22ActiveComponentFormat = ACF_XYZW,
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.Attribute23ActiveComponentFormat = ACF_XYZW,
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.Attribute24ActiveComponentFormat = ACF_XYZW,
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.Attribute25ActiveComponentFormat = ACF_XYZW,
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.Attribute26ActiveComponentFormat = ACF_XYZW,
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.Attribute27ActiveComponentFormat = ACF_XYZW,
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.Attribute28ActiveComponentFormat = ACF_XYZW,
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.Attribute29ActiveComponentFormat = ACF_XYZW,
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.Attribute28ActiveComponentFormat = ACF_XYZW,
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.Attribute29ActiveComponentFormat = ACF_XYZW,
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.Attribute30ActiveComponentFormat = ACF_XYZW,
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#endif
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};
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#if GEN_GEN >= 8
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/* On Broadwell, they broke 3DSTATE_SBE into two packets */
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struct GENX(3DSTATE_SBE_SWIZ) swiz = {
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GENX(3DSTATE_SBE_SWIZ_header),
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};
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#else
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# define swiz sbe
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#endif
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int max_source_attr = 0;
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for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
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int input_index = wm_prog_data->urb_setup[attr];
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if (input_index < 0)
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continue;
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const int slot = fs_input_map->varying_to_slot[attr];
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if (input_index >= 16)
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continue;
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if (slot == -1) {
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/* This attribute does not exist in the VUE--that means that the
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* vertex shader did not write to it. It could be that it's a
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* regular varying read by the fragment shader but not written by
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* the vertex shader or it's gl_PrimitiveID. In the first case the
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* value is undefined, in the second it needs to be
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* gl_PrimitiveID.
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*/
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swiz.Attribute[input_index].ConstantSource = PRIM_ID;
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swiz.Attribute[input_index].ComponentOverrideX = true;
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swiz.Attribute[input_index].ComponentOverrideY = true;
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swiz.Attribute[input_index].ComponentOverrideZ = true;
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swiz.Attribute[input_index].ComponentOverrideW = true;
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} else {
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assert(slot >= 2);
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const int source_attr = slot - 2;
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max_source_attr = MAX2(max_source_attr, source_attr);
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/* We have to subtract two slots to accout for the URB entry output
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* read offset in the VS and GS stages.
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*/
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swiz.Attribute[input_index].SourceAttribute = source_attr;
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}
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}
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sbe.VertexURBEntryReadOffset = 1; /* Skip the VUE header and position slots */
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sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2);
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uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
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GENX(3DSTATE_SBE_length));
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GENX(3DSTATE_SBE_pack)(&pipeline->batch, dw, &sbe);
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#if GEN_GEN >= 8
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dw = anv_batch_emit_dwords(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ_length));
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GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
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#endif
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}
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static inline uint32_t
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scratch_space(const struct brw_stage_prog_data *prog_data)
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{
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return ffs(prog_data->total_scratch / 2048);
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}
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static const uint32_t vk_to_gen_cullmode[] = {
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[VK_CULL_MODE_NONE] = CULLMODE_NONE,
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[VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
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[VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
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[VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
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};
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static const uint32_t vk_to_gen_fillmode[] = {
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[VK_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
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[VK_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
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[VK_POLYGON_MODE_POINT] = FILL_MODE_POINT,
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};
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static const uint32_t vk_to_gen_front_face[] = {
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[VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
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[VK_FRONT_FACE_CLOCKWISE] = 0
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};
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static const uint32_t vk_to_gen_logic_op[] = {
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[VK_LOGIC_OP_COPY] = LOGICOP_COPY,
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[VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
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[VK_LOGIC_OP_AND] = LOGICOP_AND,
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[VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
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[VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
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[VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
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[VK_LOGIC_OP_XOR] = LOGICOP_XOR,
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[VK_LOGIC_OP_OR] = LOGICOP_OR,
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[VK_LOGIC_OP_NOR] = LOGICOP_NOR,
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[VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
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[VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
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[VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
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[VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
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[VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
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[VK_LOGIC_OP_NAND] = LOGICOP_NAND,
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[VK_LOGIC_OP_SET] = LOGICOP_SET,
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};
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static const uint32_t vk_to_gen_blend[] = {
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[VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
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[VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
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[VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
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[VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
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[VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
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[VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
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[VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
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[VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
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[VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
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[VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
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[VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
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[VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
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[VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
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[VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
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[VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
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[VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
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[VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
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[VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
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[VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
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};
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static const uint32_t vk_to_gen_blend_op[] = {
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[VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
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[VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
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[VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
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[VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
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[VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
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};
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|
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static const uint32_t vk_to_gen_compare_op[] = {
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[VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
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[VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
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[VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
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[VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
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|
[VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
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|
[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
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[VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
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[VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
|
|
};
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|
|
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static const uint32_t vk_to_gen_stencil_op[] = {
|
|
[VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
|
|
[VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
|
|
[VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
|
|
[VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
|
|
[VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
|
|
[VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
|
|
[VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
|
|
[VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
|
|
};
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