18d51831a8
radeonsi won't emit tess factor in the lower pass, need to keep the output for llvm backend to pass it as parameter. This is used by radeonsi for an optimization to save LDS write. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
172 lines
6.1 KiB
C
172 lines
6.1 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef AC_NIR_H
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#define AC_NIR_H
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#include "nir.h"
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#include "ac_shader_args.h"
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#include "ac_shader_util.h"
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#include "amd_family.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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/* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
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AC_EXP_PARAM_OFFSET_0 = 0,
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AC_EXP_PARAM_OFFSET_31 = 31,
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/* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
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AC_EXP_PARAM_DEFAULT_VAL_0000 = 64,
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AC_EXP_PARAM_DEFAULT_VAL_0001,
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AC_EXP_PARAM_DEFAULT_VAL_1110,
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AC_EXP_PARAM_DEFAULT_VAL_1111,
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AC_EXP_PARAM_UNDEFINED = 255, /* deprecated, use AC_EXP_PARAM_DEFAULT_VAL_0000 instead */
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};
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/* Maps I/O semantics to the actual location used by the lowering pass. */
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typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
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/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
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struct nir_builder;
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typedef struct nir_builder nir_builder;
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nir_ssa_def *
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ac_nir_load_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg);
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nir_ssa_def *
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ac_nir_calc_io_offset(nir_builder *b,
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nir_intrinsic_instr *intrin,
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nir_ssa_def *base_stride,
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unsigned component_stride,
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ac_nir_map_io_driver_location map_io);
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bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
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uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]);
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void
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ac_nir_lower_ls_outputs_to_mem(nir_shader *ls,
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ac_nir_map_io_driver_location map,
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bool tcs_in_out_eq,
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uint64_t tcs_temp_only_inputs);
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void
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ac_nir_lower_hs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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bool tcs_in_out_eq);
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void
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ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool tes_reads_tessfactors,
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uint64_t tes_inputs_read,
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uint64_t tes_patch_inputs_read,
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unsigned num_reserved_tcs_outputs,
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unsigned num_reserved_tcs_patch_outputs,
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bool pass_tessfactors_by_reg,
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bool emit_tess_factor_write);
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void
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ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map);
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void
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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unsigned num_reserved_es_outputs);
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void
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ac_nir_lower_gs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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unsigned num_reserved_es_outputs);
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bool
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ac_nir_lower_indirect_derefs(nir_shader *shader,
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enum amd_gfx_level gfx_level);
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void
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ac_nir_lower_ngg_nogs(nir_shader *shader,
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enum radeon_family family,
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unsigned max_num_es_vertices,
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unsigned num_vertices_per_primitive,
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unsigned max_workgroup_size,
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unsigned wave_size,
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bool can_cull,
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bool early_prim_export,
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bool passthrough,
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bool export_prim_id,
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bool provoking_vtx_last,
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bool use_edgeflags,
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bool has_prim_query,
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uint32_t instance_rate_inputs);
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void
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ac_nir_lower_ngg_gs(nir_shader *shader,
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unsigned wave_size,
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unsigned max_workgroup_size,
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unsigned esgs_ring_lds_bytes,
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unsigned gs_out_vtx_bytes,
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unsigned gs_total_out_vtx_bytes,
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bool provoking_vtx_last);
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void
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ac_nir_lower_ngg_ms(nir_shader *shader,
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bool *out_needs_scratch_ring,
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unsigned wave_size,
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bool multiview);
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void
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ac_nir_apply_first_task_to_task_shader(nir_shader *shader);
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void
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ac_nir_lower_task_outputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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void
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ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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nir_ssa_def *
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ac_nir_cull_triangle(nir_builder *b,
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nir_ssa_def *initially_accepted,
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nir_ssa_def *pos[3][4]);
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bool
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ac_nir_lower_global_access(nir_shader *shader);
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC_NIR_H */
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