14781e2122
Right now, all keys have two things in common: a program string ID and a sampler_prog_key_data. I'd like to add another thing or two and need a place to put it. This commit adds a new brw_base_prog_key struct which contains those two common bits. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
266 lines
11 KiB
C
266 lines
11 KiB
C
/*
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* Copyright © 2015-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_compiler.h"
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#include "brw_shader.h"
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#include "brw_eu.h"
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#include "dev/gen_debug.h"
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#include "compiler/nir/nir.h"
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#include "main/errors.h"
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#include "util/debug.h"
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#define COMMON_OPTIONS \
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.lower_sub = true, \
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.lower_fdiv = true, \
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.lower_scmp = true, \
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.lower_flrp16 = true, \
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.lower_fmod = true, \
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.lower_bitfield_extract = true, \
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.lower_bitfield_insert = true, \
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.lower_uadd_carry = true, \
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.lower_usub_borrow = true, \
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.lower_fdiv = true, \
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.lower_flrp64 = true, \
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.lower_isign = true, \
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.lower_ldexp = true, \
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.lower_device_index_to_zero = true, \
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.vectorize_io = true, \
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.use_interpolated_input_intrinsics = true, \
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.vertex_id_zero_based = true, \
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.lower_base_vertex = true
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#define COMMON_SCALAR_OPTIONS \
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.lower_pack_half_2x16 = true, \
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.lower_pack_snorm_2x16 = true, \
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.lower_pack_snorm_4x8 = true, \
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.lower_pack_unorm_2x16 = true, \
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.lower_pack_unorm_4x8 = true, \
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.lower_unpack_half_2x16 = true, \
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.lower_unpack_snorm_2x16 = true, \
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.lower_unpack_snorm_4x8 = true, \
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.lower_unpack_unorm_2x16 = true, \
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.lower_unpack_unorm_4x8 = true, \
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.max_unroll_iterations = 32
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static const struct nir_shader_compiler_options scalar_nir_options = {
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COMMON_OPTIONS,
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COMMON_SCALAR_OPTIONS,
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};
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static const struct nir_shader_compiler_options vector_nir_options = {
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COMMON_OPTIONS,
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/* In the vec4 backend, our dpN instruction replicates its result to all the
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* components of a vec4. We would like NIR to give us replicated fdot
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* instructions because it can optimize better for us.
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*/
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.fdot_replicates = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.max_unroll_iterations = 32,
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};
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struct brw_compiler *
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brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
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{
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struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
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compiler->devinfo = devinfo;
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brw_fs_alloc_reg_sets(compiler);
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brw_vec4_alloc_reg_set(compiler);
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brw_init_compaction_tables(devinfo);
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compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
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compiler->use_tcs_8_patch =
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devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH);
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if (devinfo->gen >= 10) {
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/* We don't support vec4 mode on Cannonlake. */
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for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
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compiler->scalar_stage[i] = true;
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} else {
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compiler->scalar_stage[MESA_SHADER_VERTEX] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
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compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
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compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
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compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
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compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
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compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
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}
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nir_lower_int64_options int64_options =
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nir_lower_imul64 |
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nir_lower_isign64 |
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nir_lower_divmod64 |
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nir_lower_imul_high64;
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nir_lower_doubles_options fp64_options =
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nir_lower_drcp |
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nir_lower_dsqrt |
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nir_lower_drsq |
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nir_lower_dtrunc |
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nir_lower_dfloor |
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nir_lower_dceil |
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nir_lower_dfract |
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nir_lower_dround_even |
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nir_lower_dmod;
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if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) {
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int64_options |= nir_lower_mov64 |
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nir_lower_icmp64 |
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nir_lower_iadd64 |
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nir_lower_iabs64 |
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nir_lower_ineg64 |
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nir_lower_logic64 |
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nir_lower_minmax64 |
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nir_lower_shift64;
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fp64_options |= nir_lower_fp64_full_software;
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}
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/* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
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* destination type can be Quadword and source type Doubleword for Gen8 and
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* Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
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*/
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if (devinfo->gen < 8 || devinfo->gen > 9)
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int64_options |= nir_lower_imul_2x32_64;
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/* We want the GLSL compiler to emit code that uses condition codes */
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for (int i = 0; i < MESA_SHADER_STAGES; i++) {
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compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
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compiler->glsl_compiler_options[i].MaxIfDepth =
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devinfo->gen < 6 ? 16 : UINT_MAX;
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compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
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compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
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bool is_scalar = compiler->scalar_stage[i];
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compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
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compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
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compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
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struct nir_shader_compiler_options *nir_options =
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rzalloc(compiler, struct nir_shader_compiler_options);
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if (is_scalar) {
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*nir_options = scalar_nir_options;
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} else {
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*nir_options = vector_nir_options;
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}
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/* Prior to Gen6, there are no three source operations, and Gen11 loses
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* LRP.
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*/
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nir_options->lower_ffma = devinfo->gen < 6;
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nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
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nir_options->lower_rotate = devinfo->gen < 11;
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nir_options->lower_int64_options = int64_options;
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nir_options->lower_doubles_options = fp64_options;
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compiler->glsl_compiler_options[i].NirOptions = nir_options;
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compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
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}
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compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
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compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
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compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
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if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
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compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
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return compiler;
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}
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static void
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insert_u64_bit(uint64_t *val, bool add)
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{
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*val = (*val << 1) | !!add;
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}
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uint64_t
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brw_get_compiler_config_value(const struct brw_compiler *compiler)
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{
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uint64_t config = 0;
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insert_u64_bit(&config, compiler->precise_trig);
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if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
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insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
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insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
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insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
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insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
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}
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uint64_t debug_bits = INTEL_DEBUG;
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uint64_t mask = DEBUG_DISK_CACHE_MASK;
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while (mask != 0) {
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const uint64_t bit = 1ULL << (ffsll(mask) - 1);
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insert_u64_bit(&config, (debug_bits & bit) != 0);
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mask &= ~bit;
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}
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return config;
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}
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unsigned
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brw_prog_data_size(gl_shader_stage stage)
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{
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STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
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STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
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STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
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STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
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STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
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STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
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static const size_t stage_sizes[] = {
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sizeof(struct brw_vs_prog_data),
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sizeof(struct brw_tcs_prog_data),
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sizeof(struct brw_tes_prog_data),
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sizeof(struct brw_gs_prog_data),
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sizeof(struct brw_wm_prog_data),
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sizeof(struct brw_cs_prog_data),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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unsigned
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brw_prog_key_size(gl_shader_stage stage)
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{
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static const size_t stage_sizes[] = {
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sizeof(struct brw_vs_prog_key),
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sizeof(struct brw_tcs_prog_key),
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sizeof(struct brw_tes_prog_key),
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sizeof(struct brw_gs_prog_key),
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sizeof(struct brw_wm_prog_key),
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sizeof(struct brw_cs_prog_key),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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