27f0c3c15e
load_fragcoord is already handled in common code for radeonsi, so we don't need to do anything to handle it. However, there were some passes creating NIR with the varying, so we switch them over to the sysval. In the case of nir_lower_input_attachments which is used by both radv and anv, we add handling for both until intel switches to using a sysval. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
1244 lines
41 KiB
C
1244 lines
41 KiB
C
/*
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* Copyright © 2016 Dave Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "nir/nir_builder.h"
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#include "sid.h"
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#include "vk_format.h"
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static nir_shader *
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build_nir_vertex_shader(void)
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{
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const struct glsl_type *vec4 = glsl_vec4_type();
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nir_builder b;
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, "meta_resolve_vs");
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nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
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vec4, "gl_Position");
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pos_out->data.location = VARYING_SLOT_POS;
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nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
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nir_store_var(&b, pos_out, outvec, 0xf);
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return b.shader;
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}
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static nir_shader *
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build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples)
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{
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nir_builder b;
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char name[64];
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const struct glsl_type *vec4 = glsl_vec4_type();
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
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false,
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false,
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GLSL_TYPE_FLOAT);
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snprintf(name, 64, "meta_resolve_fs-%d-%s", samples, is_integer ? "int" : "float");
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, name);
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
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vec4, "f_color");
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color_out->data.location = FRAG_RESULT_DATA0;
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nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
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nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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nir_intrinsic_set_base(src_offset, 0);
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nir_intrinsic_set_range(src_offset, 8);
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src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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src_offset->num_components = 2;
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nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
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nir_builder_instr_insert(&b, &src_offset->instr);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
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nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
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radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
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color, img_coord);
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nir_ssa_def *outval = nir_load_var(&b, color);
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nir_store_var(&b, color_out, outval, 0xf);
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return b.shader;
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}
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static VkResult
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create_layout(struct radv_device *device)
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{
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VkResult result;
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/*
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* one descriptors for the image being sampled
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 1,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_fragment.ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_fragment.p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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return VK_SUCCESS;
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fail:
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return result;
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}
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static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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.vertexBindingDescriptionCount = 0,
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.vertexAttributeDescriptionCount = 0,
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};
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static VkResult
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create_resolve_pipeline(struct radv_device *device,
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int samples_log2,
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VkFormat format)
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{
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mtx_lock(&device->meta_state.mtx);
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unsigned fs_key = radv_format_meta_fs_key(format);
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VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
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if (*pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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VkResult result;
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bool is_integer = false;
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uint32_t samples = 1 << samples_log2;
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const VkPipelineVertexInputStateCreateInfo *vi_create_info;
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vi_create_info = &normal_vi_create_info;
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if (vk_format_is_int(format))
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is_integer = true;
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struct radv_shader_module fs = { .nir = NULL };
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fs.nir = build_resolve_fragment_shader(device, is_integer, samples);
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struct radv_shader_module vs = {
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.nir = build_nir_vertex_shader(),
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};
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VkRenderPass *rp = &device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][0];
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assert(!*rp);
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VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = radv_shader_module_to_handle(&vs),
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.pName = "main",
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.pSpecializationInfo = NULL
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}, {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = radv_shader_module_to_handle(&fs),
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.pName = "main",
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.pSpecializationInfo = NULL
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},
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};
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for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
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VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
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result = radv_CreateRenderPass(radv_device_to_handle(device),
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&(VkRenderPassCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
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.attachmentCount = 1,
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.pAttachments = &(VkAttachmentDescription) {
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.format = format,
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.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
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.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
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.initialLayout = layout,
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.finalLayout = layout,
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},
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.subpassCount = 1,
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.pSubpasses = &(VkSubpassDescription) {
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.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
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.inputAttachmentCount = 0,
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.colorAttachmentCount = 1,
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.pColorAttachments = &(VkAttachmentReference) {
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.attachment = 0,
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.layout = layout,
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},
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.pResolveAttachments = NULL,
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.pDepthStencilAttachment = &(VkAttachmentReference) {
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.attachment = VK_ATTACHMENT_UNUSED,
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.layout = VK_IMAGE_LAYOUT_GENERAL,
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},
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.preserveAttachmentCount = 0,
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.pPreserveAttachments = NULL,
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},
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.dependencyCount = 0,
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}, &device->meta_state.alloc, rp + dst_layout);
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}
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const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.stageCount = ARRAY_SIZE(pipeline_shader_stages),
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.pStages = pipeline_shader_stages,
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.pVertexInputState = vi_create_info,
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.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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},
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.pViewportState = &(VkPipelineViewportStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
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},
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.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = 1,
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.sampleShadingEnable = false,
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.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
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},
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.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.attachmentCount = 1,
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.pAttachments = (VkPipelineColorBlendAttachmentState []) {
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{ .colorWriteMask =
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VK_COLOR_COMPONENT_A_BIT |
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VK_COLOR_COMPONENT_R_BIT |
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VK_COLOR_COMPONENT_G_BIT |
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VK_COLOR_COMPONENT_B_BIT },
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}
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},
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.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 9,
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.pDynamicStates = (VkDynamicState[]) {
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_LINE_WIDTH,
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VK_DYNAMIC_STATE_DEPTH_BIAS,
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VK_DYNAMIC_STATE_BLEND_CONSTANTS,
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VK_DYNAMIC_STATE_DEPTH_BOUNDS,
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VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
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VK_DYNAMIC_STATE_STENCIL_REFERENCE,
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},
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},
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.flags = 0,
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.layout = device->meta_state.resolve_fragment.p_layout,
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.renderPass = *rp,
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.subpass = 0,
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};
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const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
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.use_rectlist = true
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};
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result = radv_graphics_pipeline_create(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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&vk_pipeline_info, &radv_pipeline_info,
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&device->meta_state.alloc,
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pipeline);
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ralloc_free(vs.nir);
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ralloc_free(fs.nir);
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mtx_unlock(&device->meta_state.mtx);
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return result;
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}
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enum {
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DEPTH_RESOLVE,
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STENCIL_RESOLVE
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};
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static const char *
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get_resolve_mode_str(VkResolveModeFlagBitsKHR resolve_mode)
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{
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
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return "zero";
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case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
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return "average";
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case VK_RESOLVE_MODE_MIN_BIT_KHR:
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return "min";
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case VK_RESOLVE_MODE_MAX_BIT_KHR:
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return "max";
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default:
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unreachable("invalid resolve mode");
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}
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}
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static nir_shader *
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build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
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int index,
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VkResolveModeFlagBitsKHR resolve_mode)
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{
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nir_builder b;
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char name[64];
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const struct glsl_type *vec4 = glsl_vec4_type();
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
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false,
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false,
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GLSL_TYPE_FLOAT);
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snprintf(name, 64, "meta_resolve_fs_%s-%s-%d",
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index == DEPTH_RESOLVE ? "depth" : "stencil",
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get_resolve_mode_str(resolve_mode), samples);
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
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b.shader->info.name = ralloc_strdup(b.shader, name);
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *fs_out = nir_variable_create(b.shader,
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nir_var_shader_out, vec4,
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"f_out");
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fs_out->data.location =
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index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
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nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
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nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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nir_intrinsic_set_base(src_offset, 0);
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nir_intrinsic_set_range(src_offset, 8);
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src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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src_offset->num_components = 2;
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nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
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nir_builder_instr_insert(&b, &src_offset->instr);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float : nir_type_uint;
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(img_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = type;
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tex->is_array = false;
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tex->coord_components = 2;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_ssa_def *outval = &tex->dest.ssa;
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if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
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for (int i = 1; i < samples; i++) {
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nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
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tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_add->op = nir_texop_txf_ms;
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tex_add->src[0].src_type = nir_tex_src_coord;
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tex_add->src[0].src = nir_src_for_ssa(img_coord);
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tex_add->src[1].src_type = nir_tex_src_ms_index;
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tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex_add->src[2].src_type = nir_tex_src_texture_deref;
|
|
tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
|
|
tex_add->dest_type = type;
|
|
tex_add->is_array = false;
|
|
tex_add->coord_components = 2;
|
|
|
|
nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
|
|
nir_builder_instr_insert(&b, &tex_add->instr);
|
|
|
|
switch (resolve_mode) {
|
|
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
|
|
assert(index == DEPTH_RESOLVE);
|
|
outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
|
|
break;
|
|
case VK_RESOLVE_MODE_MIN_BIT_KHR:
|
|
if (index == DEPTH_RESOLVE)
|
|
outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
|
|
else
|
|
outval = nir_umin(&b, outval, &tex_add->dest.ssa);
|
|
break;
|
|
case VK_RESOLVE_MODE_MAX_BIT_KHR:
|
|
if (index == DEPTH_RESOLVE)
|
|
outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
|
|
else
|
|
outval = nir_umax(&b, outval, &tex_add->dest.ssa);
|
|
break;
|
|
default:
|
|
unreachable("invalid resolve mode");
|
|
}
|
|
}
|
|
|
|
if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT_KHR)
|
|
outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
|
|
}
|
|
|
|
nir_store_var(&b, fs_out, outval, 0x1);
|
|
|
|
return b.shader;
|
|
}
|
|
|
|
static VkResult
|
|
create_depth_stencil_resolve_pipeline(struct radv_device *device,
|
|
int samples_log2,
|
|
int index,
|
|
VkResolveModeFlagBitsKHR resolve_mode)
|
|
{
|
|
VkRenderPass *render_pass;
|
|
VkPipeline *pipeline;
|
|
VkFormat src_format;
|
|
VkResult result;
|
|
|
|
mtx_lock(&device->meta_state.mtx);
|
|
|
|
switch (resolve_mode) {
|
|
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
|
|
if (index == DEPTH_RESOLVE)
|
|
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
|
|
assert(index == DEPTH_RESOLVE);
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MIN_BIT_KHR:
|
|
if (index == DEPTH_RESOLVE)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MAX_BIT_KHR:
|
|
if (index == DEPTH_RESOLVE)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
|
|
break;
|
|
default:
|
|
unreachable("invalid resolve mode");
|
|
}
|
|
|
|
if (*pipeline) {
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
struct radv_shader_module fs = { .nir = NULL };
|
|
struct radv_shader_module vs = { .nir = NULL };
|
|
uint32_t samples = 1 << samples_log2;
|
|
|
|
vs.nir = build_nir_vertex_shader();
|
|
fs.nir = build_depth_stencil_resolve_fragment_shader(device, samples,
|
|
index, resolve_mode);
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
|
|
{
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
.stage = VK_SHADER_STAGE_VERTEX_BIT,
|
|
.module = radv_shader_module_to_handle(&vs),
|
|
.pName = "main",
|
|
.pSpecializationInfo = NULL
|
|
}, {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
|
|
.module = radv_shader_module_to_handle(&fs),
|
|
.pName = "main",
|
|
.pSpecializationInfo = NULL
|
|
},
|
|
};
|
|
|
|
if (index == DEPTH_RESOLVE) {
|
|
src_format = VK_FORMAT_D32_SFLOAT;
|
|
render_pass = &device->meta_state.resolve_fragment.depth_render_pass;
|
|
} else {
|
|
render_pass = &device->meta_state.resolve_fragment.stencil_render_pass;
|
|
src_format = VK_FORMAT_S8_UINT;
|
|
}
|
|
|
|
if (!*render_pass) {
|
|
result = radv_CreateRenderPass(radv_device_to_handle(device),
|
|
&(VkRenderPassCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
|
|
.attachmentCount = 1,
|
|
.pAttachments = &(VkAttachmentDescription) {
|
|
.format = src_format,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
|
|
.storeOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE,
|
|
.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
.subpassCount = 1,
|
|
.pSubpasses = &(VkSubpassDescription) {
|
|
.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
.inputAttachmentCount = 0,
|
|
.colorAttachmentCount = 0,
|
|
.pColorAttachments = NULL,
|
|
.pResolveAttachments = NULL,
|
|
.pDepthStencilAttachment = &(VkAttachmentReference) {
|
|
.attachment = 0,
|
|
.layout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
.preserveAttachmentCount = 0,
|
|
.pPreserveAttachments = NULL,
|
|
},
|
|
.dependencyCount = 0,
|
|
}, &device->meta_state.alloc, render_pass);
|
|
}
|
|
|
|
VkStencilOp stencil_op =
|
|
index == DEPTH_RESOLVE ? VK_STENCIL_OP_KEEP : VK_STENCIL_OP_REPLACE;
|
|
|
|
VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
|
|
.depthTestEnable = true,
|
|
.depthWriteEnable = index == DEPTH_RESOLVE,
|
|
.stencilTestEnable = index == STENCIL_RESOLVE,
|
|
.depthCompareOp = VK_COMPARE_OP_ALWAYS,
|
|
.front = {
|
|
.failOp = stencil_op,
|
|
.passOp = stencil_op,
|
|
.depthFailOp = stencil_op,
|
|
.compareOp = VK_COMPARE_OP_ALWAYS,
|
|
},
|
|
.back = {
|
|
.failOp = stencil_op,
|
|
.passOp = stencil_op,
|
|
.depthFailOp = stencil_op,
|
|
.compareOp = VK_COMPARE_OP_ALWAYS,
|
|
}
|
|
};
|
|
|
|
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
|
|
vi_create_info = &normal_vi_create_info;
|
|
|
|
const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
|
|
.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
|
|
.stageCount = ARRAY_SIZE(pipeline_shader_stages),
|
|
.pStages = pipeline_shader_stages,
|
|
.pVertexInputState = vi_create_info,
|
|
.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
|
|
.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
|
|
.primitiveRestartEnable = false,
|
|
},
|
|
.pViewportState = &(VkPipelineViewportStateCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
|
|
.viewportCount = 1,
|
|
.scissorCount = 1,
|
|
},
|
|
.pDepthStencilState = &depth_stencil_state,
|
|
.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
|
|
.rasterizerDiscardEnable = false,
|
|
.polygonMode = VK_POLYGON_MODE_FILL,
|
|
.cullMode = VK_CULL_MODE_NONE,
|
|
.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
|
|
},
|
|
.pMultisampleState = NULL,
|
|
.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
|
|
.attachmentCount = 0,
|
|
.pAttachments = (VkPipelineColorBlendAttachmentState []) {
|
|
{ .colorWriteMask =
|
|
VK_COLOR_COMPONENT_A_BIT |
|
|
VK_COLOR_COMPONENT_R_BIT |
|
|
VK_COLOR_COMPONENT_G_BIT |
|
|
VK_COLOR_COMPONENT_B_BIT },
|
|
}
|
|
},
|
|
.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
|
|
.dynamicStateCount = 9,
|
|
.pDynamicStates = (VkDynamicState[]) {
|
|
VK_DYNAMIC_STATE_VIEWPORT,
|
|
VK_DYNAMIC_STATE_SCISSOR,
|
|
VK_DYNAMIC_STATE_LINE_WIDTH,
|
|
VK_DYNAMIC_STATE_DEPTH_BIAS,
|
|
VK_DYNAMIC_STATE_BLEND_CONSTANTS,
|
|
VK_DYNAMIC_STATE_DEPTH_BOUNDS,
|
|
VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
|
|
VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
|
|
VK_DYNAMIC_STATE_STENCIL_REFERENCE,
|
|
},
|
|
},
|
|
.flags = 0,
|
|
.layout = device->meta_state.resolve_fragment.p_layout,
|
|
.renderPass = *render_pass,
|
|
.subpass = 0,
|
|
};
|
|
|
|
const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
|
|
.use_rectlist = true
|
|
};
|
|
|
|
result = radv_graphics_pipeline_create(radv_device_to_handle(device),
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache),
|
|
&vk_pipeline_info, &radv_pipeline_info,
|
|
&device->meta_state.alloc,
|
|
pipeline);
|
|
|
|
ralloc_free(vs.nir);
|
|
ralloc_free(fs.nir);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
return result;
|
|
}
|
|
|
|
VkResult
|
|
radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand)
|
|
{
|
|
VkResult res;
|
|
|
|
res = create_layout(device);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
if (on_demand)
|
|
return VK_SUCCESS;
|
|
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
|
res = create_resolve_pipeline(device, i, radv_fs_key_format_exemplars[j]);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
}
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_AVERAGE_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_MIN_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_MAX_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_MIN_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_MAX_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
}
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
|
|
if (res != VK_SUCCESS)
|
|
goto fail;
|
|
|
|
return VK_SUCCESS;
|
|
fail:
|
|
radv_device_finish_meta_resolve_fragment_state(device);
|
|
return res;
|
|
}
|
|
|
|
void
|
|
radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
|
|
{
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
|
for(unsigned k =0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
|
|
radv_DestroyRenderPass(radv_device_to_handle(device),
|
|
state->resolve_fragment.rc[i].render_pass[j][k],
|
|
&state->alloc);
|
|
}
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.rc[i].pipeline[j],
|
|
&state->alloc);
|
|
}
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].average_pipeline,
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].max_pipeline,
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].min_pipeline,
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil[i].max_pipeline,
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil[i].min_pipeline,
|
|
&state->alloc);
|
|
}
|
|
|
|
radv_DestroyRenderPass(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth_render_pass,
|
|
&state->alloc);
|
|
radv_DestroyRenderPass(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil_render_pass,
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth_zero_pipeline,
|
|
&state->alloc);
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil_zero_pipeline,
|
|
&state->alloc);
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
|
|
state->resolve_fragment.ds_layout,
|
|
&state->alloc);
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device),
|
|
state->resolve_fragment.p_layout,
|
|
&state->alloc);
|
|
}
|
|
|
|
static VkPipeline *
|
|
radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image_view *src_iview,
|
|
struct radv_image_view *dst_iview)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
unsigned fs_key = radv_format_meta_fs_key(dst_iview->vk_format);
|
|
const uint32_t samples = src_iview->image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
VkPipeline *pipeline;
|
|
|
|
pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
|
|
if (!*pipeline ) {
|
|
VkResult ret;
|
|
|
|
ret = create_resolve_pipeline(device, samples_log2,
|
|
radv_fs_key_format_exemplars[fs_key]);
|
|
if (ret != VK_SUCCESS) {
|
|
cmd_buffer->record_result = ret;
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
return pipeline;
|
|
}
|
|
|
|
static void
|
|
emit_resolve(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image_view *src_iview,
|
|
struct radv_image_view *dest_iview,
|
|
const VkOffset2D *src_offset,
|
|
const VkOffset2D *dest_offset,
|
|
const VkExtent2D *resolve_extent)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
|
|
VkPipeline *pipeline;
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
cmd_buffer->device->meta_state.resolve_fragment.p_layout,
|
|
0, /* set */
|
|
1, /* descriptorWriteCount */
|
|
(VkWriteDescriptorSet[]) {
|
|
{
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 0,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}
|
|
},
|
|
});
|
|
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
|
|
|
|
unsigned push_constants[2] = {
|
|
src_offset->x - dest_offset->x,
|
|
src_offset->y - dest_offset->y,
|
|
};
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
device->meta_state.resolve_fragment.p_layout,
|
|
VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
|
|
push_constants);
|
|
|
|
pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview, dest_iview);
|
|
|
|
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
*pipeline);
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
|
|
.x = dest_offset->x,
|
|
.y = dest_offset->y,
|
|
.width = resolve_extent->width,
|
|
.height = resolve_extent->height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f
|
|
});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
|
|
.offset = *dest_offset,
|
|
.extent = *resolve_extent,
|
|
});
|
|
|
|
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
|
|
}
|
|
|
|
static void
|
|
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image_view *src_iview,
|
|
struct radv_image_view *dst_iview,
|
|
const VkOffset2D *src_offset,
|
|
const VkOffset2D *dst_offset,
|
|
const VkExtent2D *resolve_extent,
|
|
VkImageAspectFlags aspects,
|
|
VkResolveModeFlagBitsKHR resolve_mode)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
const uint32_t samples = src_iview->image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
VkPipeline *pipeline;
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer,
|
|
VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
cmd_buffer->device->meta_state.resolve_fragment.p_layout,
|
|
0, /* set */
|
|
1, /* descriptorWriteCount */
|
|
(VkWriteDescriptorSet[]) {
|
|
{
|
|
.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 0,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
.pImageInfo = (VkDescriptorImageInfo[]) {
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}
|
|
},
|
|
});
|
|
|
|
unsigned push_constants[2] = {
|
|
src_offset->x - dst_offset->x,
|
|
src_offset->y - dst_offset->y,
|
|
};
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
device->meta_state.resolve_fragment.p_layout,
|
|
VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8,
|
|
push_constants);
|
|
|
|
switch (resolve_mode) {
|
|
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
|
|
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MIN_BIT_KHR:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MAX_BIT_KHR:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
|
|
break;
|
|
default:
|
|
unreachable("invalid resolve mode");
|
|
}
|
|
|
|
if (!*pipeline) {
|
|
int index = aspects == VK_IMAGE_ASPECT_DEPTH_BIT ? DEPTH_RESOLVE : STENCIL_RESOLVE;
|
|
VkResult ret;
|
|
|
|
ret = create_depth_stencil_resolve_pipeline(device, samples_log2,
|
|
index, resolve_mode);
|
|
if (ret != VK_SUCCESS) {
|
|
cmd_buffer->record_result = ret;
|
|
return;
|
|
}
|
|
}
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
|
|
.x = dst_offset->x,
|
|
.y = dst_offset->y,
|
|
.width = resolve_extent->width,
|
|
.height = resolve_extent->height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f
|
|
});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
|
|
.offset = *dst_offset,
|
|
.extent = *resolve_extent,
|
|
});
|
|
|
|
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
|
}
|
|
|
|
void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radv_image *src_image,
|
|
VkImageLayout src_image_layout,
|
|
struct radv_image *dest_image,
|
|
VkImageLayout dest_image_layout,
|
|
uint32_t region_count,
|
|
const VkImageResolve *regions)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
struct radv_meta_saved_state saved_state;
|
|
const uint32_t samples = src_image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
|
|
unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
|
|
VkRenderPass rp;
|
|
|
|
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
|
|
region_count, regions);
|
|
|
|
if (!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout]) {
|
|
VkResult ret = create_resolve_pipeline(device, samples_log2, radv_fs_key_format_exemplars[fs_key]);
|
|
if (ret != VK_SUCCESS) {
|
|
cmd_buffer->record_result = ret;
|
|
return;
|
|
}
|
|
}
|
|
|
|
rp = device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE |
|
|
RADV_META_SAVE_CONSTANTS |
|
|
RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
for (uint32_t r = 0; r < region_count; ++r) {
|
|
const VkImageResolve *region = ®ions[r];
|
|
|
|
assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
|
|
|
|
const uint32_t src_base_layer =
|
|
radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
|
|
®ion->srcOffset);
|
|
|
|
const uint32_t dest_base_layer =
|
|
radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource,
|
|
®ion->dstOffset);
|
|
|
|
const struct VkExtent3D extent =
|
|
radv_sanitize_image_extent(src_image->type, region->extent);
|
|
const struct VkOffset3D srcOffset =
|
|
radv_sanitize_image_offset(src_image->type, region->srcOffset);
|
|
const struct VkOffset3D dstOffset =
|
|
radv_sanitize_image_offset(dest_image->type, region->dstOffset);
|
|
|
|
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
|
|
++layer) {
|
|
|
|
struct radv_image_view src_iview;
|
|
radv_image_view_init(&src_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(src_image),
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
.format = src_image->vk_format,
|
|
.subresourceRange = {
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = region->srcSubresource.mipLevel,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = src_base_layer + layer,
|
|
.layerCount = 1,
|
|
},
|
|
});
|
|
|
|
struct radv_image_view dest_iview;
|
|
radv_image_view_init(&dest_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(dest_image),
|
|
.viewType = radv_meta_get_view_type(dest_image),
|
|
.format = dest_image->vk_format,
|
|
.subresourceRange = {
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = dest_base_layer + layer,
|
|
.layerCount = 1,
|
|
},
|
|
});
|
|
|
|
|
|
VkFramebuffer fb;
|
|
radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
|
|
&(VkFramebufferCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
|
|
.attachmentCount = 1,
|
|
.pAttachments = (VkImageView[]) {
|
|
radv_image_view_to_handle(&dest_iview),
|
|
},
|
|
.width = extent.width + dstOffset.x,
|
|
.height = extent.height + dstOffset.y,
|
|
.layers = 1
|
|
}, &cmd_buffer->pool->alloc, &fb);
|
|
|
|
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
&(VkRenderPassBeginInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
|
|
.renderPass = rp,
|
|
.framebuffer = fb,
|
|
.renderArea = {
|
|
.offset = { dstOffset.x, dstOffset.y, },
|
|
.extent = { extent.width, extent.height },
|
|
},
|
|
.clearValueCount = 0,
|
|
.pClearValues = NULL,
|
|
}, VK_SUBPASS_CONTENTS_INLINE);
|
|
|
|
|
|
|
|
emit_resolve(cmd_buffer,
|
|
&src_iview,
|
|
&dest_iview,
|
|
&(VkOffset2D) { srcOffset.x, srcOffset.y },
|
|
&(VkOffset2D) { dstOffset.x, dstOffset.y },
|
|
&(VkExtent2D) { extent.width, extent.height });
|
|
|
|
radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
|
|
radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device), fb, &cmd_buffer->pool->alloc);
|
|
}
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|
|
|
|
|
|
/**
|
|
* Emit any needed resolves for the current subpass.
|
|
*/
|
|
void
|
|
radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
|
|
{
|
|
struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
struct radv_meta_saved_state saved_state;
|
|
struct radv_subpass_barrier barrier;
|
|
|
|
/* Resolves happen before the end-of-subpass barriers get executed,
|
|
* so we have to make the attachment shader-readable */
|
|
barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
|
|
barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
|
|
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
|
|
radv_subpass_barrier(cmd_buffer, &barrier);
|
|
|
|
radv_decompress_resolve_subpass_src(cmd_buffer);
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE |
|
|
RADV_META_SAVE_CONSTANTS |
|
|
RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
for (uint32_t i = 0; i < subpass->color_count; ++i) {
|
|
struct radv_subpass_attachment src_att = subpass->color_attachments[i];
|
|
struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
|
|
|
|
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
|
|
continue;
|
|
|
|
struct radv_image_view *dest_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
|
|
struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
|
|
|
|
struct radv_subpass resolve_subpass = {
|
|
.color_count = 1,
|
|
.color_attachments = (struct radv_subpass_attachment[]) { dest_att },
|
|
.depth_stencil_attachment = NULL,
|
|
};
|
|
|
|
radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
|
|
|
|
emit_resolve(cmd_buffer,
|
|
src_iview,
|
|
dest_iview,
|
|
&(VkOffset2D) { 0, 0 },
|
|
&(VkOffset2D) { 0, 0 },
|
|
&(VkExtent2D) { fb->width, fb->height });
|
|
}
|
|
|
|
radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|
|
|
|
/**
|
|
* Depth/stencil resolves for the current subpass.
|
|
*/
|
|
void
|
|
radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
|
|
VkImageAspectFlags aspects,
|
|
VkResolveModeFlagBitsKHR resolve_mode)
|
|
{
|
|
struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
struct radv_meta_saved_state saved_state;
|
|
struct radv_subpass_barrier barrier;
|
|
|
|
/* Resolves happen before the end-of-subpass barriers get executed,
|
|
* so we have to make the attachment shader-readable */
|
|
barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
|
|
barrier.src_access_mask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
|
|
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
|
|
radv_subpass_barrier(cmd_buffer, &barrier);
|
|
|
|
radv_decompress_resolve_subpass_src(cmd_buffer);
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE |
|
|
RADV_META_SAVE_CONSTANTS |
|
|
RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
|
|
struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
|
|
|
|
struct radv_image_view *src_iview =
|
|
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
|
|
struct radv_image *src_image = src_iview->image;
|
|
struct radv_image_view *dst_iview =
|
|
cmd_buffer->state.framebuffer->attachments[dst_att.attachment].attachment;
|
|
|
|
struct radv_subpass resolve_subpass = {
|
|
.color_count = 0,
|
|
.color_attachments = NULL,
|
|
.depth_stencil_attachment = (struct radv_subpass_attachment *) { &dst_att },
|
|
};
|
|
|
|
radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
|
|
|
|
struct radv_image_view tsrc_iview;
|
|
radv_image_view_init(&tsrc_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo) {
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(src_image),
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
.format = src_iview->vk_format,
|
|
.subresourceRange = {
|
|
.aspectMask = aspects,
|
|
.baseMipLevel = 0,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = 0,
|
|
.layerCount = 1,
|
|
},
|
|
});
|
|
|
|
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
|
|
&(VkOffset2D) { 0, 0 },
|
|
&(VkOffset2D) { 0, 0 },
|
|
&(VkExtent2D) { fb->width, fb->height },
|
|
aspects,
|
|
resolve_mode);
|
|
|
|
radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|