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Author SHA1 Message Date
Lionel Landwerlin
ff91c5ca42 anv: add analysis for push descriptor uses and store it in shader cache 
We'll use this information to avoid :
   - binding table emission
   - allocation of surface states

v2: Fix anv_nir_push_desc_ubo_fully_promoted()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
01e282f23f anv: initialization pipeline layout to 0s 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
8616f11a39 anv: track descriptor set layout flags 
To identify push descriptors.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
d7f1569307 anv: limit push constant reemission 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
2db45f713a isl: avoid gfx version switch cases on the hot path 
Some of the surface state packing functions are called from the hot
path in Anv. We can use function pointers to avoid repeatedly going
through switch/case.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
06d955ab21 anv: remove multiple push descriptors 
VUID-VkPipelineLayoutCreateInfo-pSetLayouts-00293

   pSetLayouts must not contain more than one descriptor set layout
   that was created with
   VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR set

There is only one push descriptor set with all the descriptor sets, so
no need to have an array.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
803f438d85 anv: optimize 3DSTATE_VF emission 
We can avoid reemitting this when the index buffer index type doesn't
change.

Also we don't need to update this when the pipeline changes as we do
not pull any value from the pipeline. Instead rely on the dynamic
state to tell if dyn->ia.primitive_restart_enable changed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
126f5bc15a anv: limit calls into cmd_buffer_flush_dynamic_state 
Avoids a bunch of checks if we can.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
54bc34f70a anv: comment out the Gfx8/9 VB cache key workaround for newer Gens 
This code shows up a little on profiling on Gfx12 and since it's only
a gfx8/9 workaround we might as well ifdef it out.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
f8136ea5b6 anv: remove unused code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Lionel Landwerlin
cea113c977 vulkan/runtime: don't lookup the pipeline disk cache if disabled 
When the Anv pipeline got migrated to the runtime, we gain/lost a bit
of functionality which is that the disk cache is always read
regardless of VK_ENABLE_PIPELINE_CACHE=0.

This change brings the old behavior back.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 591da98779 ("vulkan: Add a common VkPipelineCache implementation")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>
 2022-10-14 23:03:16 +00:00
Bas Nieuwenhuizen
6558ecf3eb radv: Mark dEQP-VK.ray_query.misc.dynamic_indexing as crashing in CI. 
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7493
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19073>
 2022-10-14 21:34:54 +00:00
Ryan Houdek
b516f59490 vulkan/wsi: Add dep_libudev to idep dependencies 
Otherwise users of `idep_vulkan_wsi` won't pull in the udev dependency,
which will cause the linker to fail later on in compiling.

The user of this dependency is lavapipe which would fail to link if this
isn't provided.

Fixes: 4885e63a6d (vulkan/wsi: implement missing wsi_register_device_event)

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19037>
 2022-10-14 21:10:29 +00:00
David Heidelberg
9cb251a0b0 ci/traces: Blender demo (Cube Diorama) flakes on Intel APL 
Acked-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19067>
 2022-10-14 18:44:30 +00:00
Gert Wollny
2e50bf19cd nir: move fusing csel and comparisons to opt_late_algebraic 
With that simple comparisons are cleaned up properly.

This helps with some tesselation shaders on r600.

Shader-db stats R600/Cayman:

--------------------------------------------------------------
total dw in shared programs: 1621806 -> 1620884 (-0.06%)
dw in affected programs: 41650 -> 40728 (-2.21%)
helped: 211
HURT: 4
helped stats (abs) min: 2 max: 26 x̄: 4.46 x̃: 4
helped stats (rel) min: 0.30% max: 9.68% x̄: 2.87% x̃: 2.52%
HURT stats (abs)   min: 2 max: 8 x̄: 5.00 x̃: 5
HURT stats (rel)   min: 0.23% max: 1.67% x̄: 1.02% x̃: 1.09%
95% mean confidence interval for dw value: -4.81 -3.77
95% mean confidence interval for dw %-change: -3.03% -2.57%
Dw are helped.

total gprs in shared programs: 41192 -> 41182 (-0.02%)
gprs in affected programs: 731 -> 721 (-1.37%)
helped: 53
HURT: 45
helped stats (abs) min: 1 max: 3 x̄: 1.23 x̃: 1
helped stats (rel) min: 5.88% max: 40.00% x̄: 16.56% x̃: 14.29%
HURT stats (abs)   min: 1 max: 2 x̄: 1.22 x̃: 1
HURT stats (rel)   min: 7.69% max: 40.00% x̄: 19.42% x̃: 20.00%
95% mean confidence interval for gprs value: -0.37 0.16
95% mean confidence interval for gprs %-change: -3.92% 3.85%
Inconclusive result (value mean confidence interval includes 0).

total alu_groups in shared programs: 203677 -> 203632 (-0.02%)
alu_groups in affected programs: 2876 -> 2831 (-1.56%)
helped: 68
HURT: 30
helped stats (abs) min: 1 max: 4 x̄: 1.46 x̃: 1
helped stats (rel) min: 0.84% max: 25.00% x̄: 7.48% x̃: 5.41%
HURT stats (abs)   min: 1 max: 6 x̄: 1.80 x̃: 1
HURT stats (rel)   min: 1.98% max: 33.33% x̄: 10.09% x̃: 5.61%
95% mean confidence interval for alu_groups value: -0.81 -0.11
95% mean confidence interval for alu_groups %-change: -4.20% <.01%
Alu_groups are helped.

total loops in shared programs: 72 -> 72 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cf in shared programs: 88230 -> 88233 (<.01%)
cf in affected programs: 71 -> 74 (4.23%)
helped: 1
HURT: 4
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.89% max: 33.33% x̄: 17.14% x̃: 16.67%
95% mean confidence interval for cf value: -0.51 1.71
95% mean confidence interval for cf %-change: -24.20% 38.29%
Inconclusive result (value mean confidence interval includes 0).

total stack in shared programs: 3827 -> 3827 (0.00%)
stack in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   0
GAINED: 0

Total CPU time (seconds): 45.32 -> 41.69 (-8.01%)
--------------------------------------------------------------

v2: Simplify replacement pattern (Rhys Perry)
v3: fix ws (Alexander Orzechowski)
v4: move the original lowering to opt_late_algebraic and
    drop cleanup code (Alyssa)
v5: Add shader-sb stats (Alyssa)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18970>
 2022-10-14 13:08:15 +00:00
Gert Wollny
aea311dbef r600/sfn: run cleanup passes after late algebraic opt 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18970>
 2022-10-14 13:08:15 +00:00
Väinö Mäkelä
cfc6bdb760 hasvk: Correctly set NonPerspectiveBarycentricEnable on gfx7 
The incorrect #else has existed since commit bfd9942cdc, but the issue
was already present before that. NonPerspectiveBarycentricEnable must be
enabled if non-perspective interpolation is used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7449
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19004>
 2022-10-14 08:18:40 +00:00
Lionel Landwerlin
eec49374b0 nir: fix NIR_DEBUG=validate_ssa_dominance 
validate_ssa_def_dominance() asserts :

   validate_assert(state, !BITSET_TEST(state->ssa_defs_found, def->index));

Because the previous validation lefts bits set when it processed the
IR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18966>
 2022-10-14 10:36:56 +03:00
Yonggang Luo
44ccaca41d util/mesa/wide: Rename _SIMPLE_MTX_INITIALIZER_NP to SIMPLE_MTX_INITIALIZER 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18393>
 2022-10-14 03:27:41 +00:00
Guilherme Gallo
be3c46964b ci/bin: Remove whitespace from token files 
There was a security problem with some `gitlab_gql.py` scenarios because
of `\r` and `\n` in the token file, which interrupted the requests for
Gitlab endpoints.

Stripping the token file after reading the file content solves the
problem.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
 2022-10-14 01:46:52 +00:00
Guilherme Gallo
d52d51b24d ci/bin: Fix requirements.txt 
Add missing aiohttp and PyYAML packages

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
 2022-10-14 01:46:52 +00:00
Alyssa Rosenzweig
bb6c43027e agx: Reserve live-in regs at the start of block 
...Rather than reserving the union of the registers live-out of the
predecessors. This avoids reserving registers that are killed along a
control flow edge (where the predecessor has another successor that does
use the register).

glmark2 subset of shaderdb:

total instructions in shared programs: 6442 -> 6440 (-0.03%)
instructions in affected programs: 42 -> 40 (-4.76%)
helped: 1
HURT: 0

total bytes in shared programs: 42186 -> 42174 (-0.03%)
bytes in affected programs: 270 -> 258 (-4.44%)
helped: 1
HURT: 0

total halfregs in shared programs: 1769 -> 1757 (-0.68%)
halfregs in affected programs: 75 -> 63 (-16.00%)
helped: 3
HURT: 0
helped stats (abs) min: 4.0 max: 4.0 x̄: 4.00 x̃: 4
helped stats (rel) min: 16.00% max: 16.00% x̄: 16.00% x̃: 16.00%

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
de6e11b848 agx: Pass in max regs as a paramter to RA 
This will allow us to restrict max regs later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
68f89d4cc5 agx: Introduce ra_ctx data structure 
We have more parameters to pass, this will get unwieldly otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
bcb2cf9688 agx: Write to r0l with a "nesting" instruction 
This avoids modeling the r0l register explicitly in the IR, which would
complicate RA for little benefit at this stage. Do the simplest thing
that could possibly work in SSA.

glmark2 subset.

total instructions in shared programs: 6442 -> 6442 (0.00%)
instructions in affected programs: 701 -> 701 (0.00%)
helped: 4
HURT: 5
helped stats (abs) min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 1.46% max: 7.69% x̄: 4.03% x̃: 3.48%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.60 x̃: 1
HURT stats (rel)   min: 0.81% max: 7.41% x̄: 2.67% x̃: 1.14%
95% mean confidence interval for instructions value: -1.58 1.58
95% mean confidence interval for instructions %-change: -3.70% 3.08%
Inconclusive result (value mean confidence interval includes 0).

total bytes in shared programs: 42196 -> 42186 (-0.02%)
bytes in affected programs: 7768 -> 7758 (-0.13%)
helped: 8
HURT: 5
helped stats (abs) min: 2.0 max: 18.0 x̄: 7.25 x̃: 4
helped stats (rel) min: 0.13% max: 7.26% x̄: 2.02% x̃: 0.97%
HURT stats (abs)   min: 6.0 max: 18.0 x̄: 9.60 x̃: 6
HURT stats (rel)   min: 0.82% max: 6.32% x̄: 2.37% x̃: 1.02%
95% mean confidence interval for bytes value: -7.02 5.48
95% mean confidence interval for bytes %-change: -2.30% 1.63%
Inconclusive result (value mean confidence interval includes 0).

total halfregs in shared programs: 1926 -> 1769 (-8.15%)
halfregs in affected programs: 1395 -> 1238 (-11.25%)
helped: 71
HURT: 0
helped stats (abs) min: 1.0 max: 10.0 x̄: 2.21 x̃: 2
helped stats (rel) min: 1.92% max: 52.63% x̄: 15.33% x̃: 11.76%
95% mean confidence interval for halfregs value: -2.69 -1.73
95% mean confidence interval for halfregs %-change: -17.98% -12.68%
Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
c9a96d4615 agx: Preload vertex/instance ID only at start 
This means we don't reserve the registers, which improves RA
considerably. Using a special preload psuedo-op instead of a regular
move allows us to constrain semantics and gaurantee coalescing.

shader-db on glmark2 subset:

total instructions in shared programs: 6448 -> 6442 (-0.09%)
instructions in affected programs: 230 -> 224 (-2.61%)
helped: 4
HURT: 0

total bytes in shared programs: 42232 -> 42196 (-0.09%)
bytes in affected programs: 1530 -> 1494 (-2.35%)
helped: 4
HURT: 0

total halfregs in shared programs: 2291 -> 1926 (-15.93%)
halfregs in affected programs: 2185 -> 1820 (-16.70%)
helped: 75
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
f665229d77 agx: Print agx_dim appropriately 
Easier to read, and gets us closer to proper disasm in Mesa.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
6c95572ef0 agx: Print instructions as "dest = src" 
This makes the dataflow easier to read, especially with splits and
collects (which take variable numbers of sources/destinations).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
72a1e1f33f agx: Emit trap at pack-time, not during isel 
This makes the shaderdb stats make more sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
1dcaade3e2 agx: Rename "combine" to "collect" 
For consistency with ir3 and bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
82e8e709cb agx: Dynamically size split instruction 
This is more flexible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
7c9fba34bc agx: Switch to dynamic allocation of srcs/dests 
So we can handle parallel copies later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
544c60a132 agx: Improve printing of immediate sources 
For floats, decode the float. Regardless, the size speciifer is
redundant.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
c2bc8c1384 agx: Don't prefix pseudo-ops 
It's not really buying us anything and it clutters the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
40f0ac2082 agx: Emit smaller combines for nir_op_vec2/3 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
f4726cf240 agx: Set PIPE_SHADER_CAP_INDIRECT_CONST_ADDR 
Avoids spilling in t-rex.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
6a183a9ffd agx: Add iterators for phi/non-phi instructions 
We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
 2022-10-14 01:37:39 +00:00
Mike Blumenkrantz
d3880a6324 zink: disable fbfetch when flushing clears 
this ensures there's no weird perf happening, avoids using renderpass
instead of dynamic rendering, and avoids hitting an assert from broken
framebuffer construction

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
 2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
1ae26de36f zink: unset rp_changed after initializing renderpass attachments 
if fbfetch is setup here, it will flag rp_changed

this is already inside renderpass setup, however, so just unset it
to avoid erroneously trigering the assert

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
 2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
f72071fbc3 zink: clamp line_stipple_factor to 1 if stipple is disabled 
0 is technically an illegal value even though it won't be read in this case

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
 2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
2710ef4c2a zink: don't add other usage bits for transient images 
this is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
 2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
3dcc03d979 zink: check core feature for pipeline cache control 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
 2022-10-14 01:16:30 +00:00
Emma Anholt
179e638bb8 zink: Fix dummy CB path decision for VK_EXT_cwe presence. 
We have to do the dummy workaround when we *don't* have the ext.  This was
apparently a mis-sedding.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19057>
 2022-10-14 00:55:36 +00:00
Karol Herbst
6a18e154bc rusticl/mem: propper CL_MEM_ALLOC_HOST_PTR support 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
7195b62c63 lp: claim being UMA 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
72f763f5cc rusticl/mem: rewrite the (un)mapping code 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
dc081353ac rusticl: add helper ctx wrapper for coherent and direct mapping 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
ea5b23c75b rusticl: rework resource mappings a little 
The _async variants will be removed later.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
6b235361f7 rusticl/mesa: add bx() method to PipeTransfer 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00
Karol Herbst
557f4dd89a rusticl: add support for coherent resources 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
 2022-10-13 23:15:33 +00:00