Commit Graph

108587 Commits

Author SHA1 Message Date
Vivek Kasireddy
ff14d06be5 drm-uapi: Update headers from drm-next
Pull new updates from drm-next as of the following commit:

commit a5f2fafece141ef3509e686cea576366d55cabb6
Merge: 71f4e45a4ed3 860433ed2a55
Author: Dave Airlie <airlied@redhat.com>
Date:   Wed Feb 20 12:16:30 2019 +1000

    Merge https://gitlab.freedesktop.org/drm/msm into drm-next

Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 13:08:51 +00:00
Kasireddy, Vivek
78fb3fd17e nir/lower_tex: Add support for XYUV lowering
The memory layout associated with this format would be:
Byte:      0 1 2 3
Component: V U Y X

Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 13:08:51 +00:00
Lionel Landwerlin
913d711e0f imgui: update memory editor
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-26 12:49:07 +00:00
Lionel Landwerlin
ab9ae080ec imgui: update commit
In commit 3950e7c11e ("imgui: bump copy") I forgot to update the
README about what copy of imgui we carry.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-26 12:49:04 +00:00
Eric Engestrom
a213b927f2 driinfo: add DTD to allow the xml to be validated
This DTD can be used to validate the output and make sure any parsers
out there can handle it:
$ xmllint --noout --valid driinfo.xml

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-26 12:48:28 +00:00
Lionel Landwerlin
9646750822 vulkan/overlay: fix includes
The Loader/Validation-Layers repository allow the user to choose where
header files are installed. On my system I choose /usr/include
thinking it was the obvious "base" location, but it turns out the
headers end up being installed right there rather in a vulkan
subdirectory. On Debian/Ubuntu the selected installation path is
/usr/include/vulkan, so just go with that.

Hopefully other distro don't choose another path.

Note that the validation layer doesn't provide a .pc file so we have
no way of querying where the headers are installed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109739
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 12:29:54 +00:00
Lionel Landwerlin
47ef52d333 vulkan/overlay: fix missing installation of layer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109739
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 12:29:46 +00:00
Eric Engestrom
318e550549 dri_interface: add missing #include
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-26 12:03:20 +00:00
Eric Engestrom
7f5d9c2757 gitlab-ci: always run the containers build
If the first time a fork was created, the job creating the containers was
manually cancelled, this would have left the fork unable to use the CI
(until the next automatic regeneration of the container).

Avoid this by always running the container-generation job, even though
99% of the time it will spin up, see that the container exists and shut
down.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2019-02-26 12:02:14 +00:00
Emil Velikov
40a82e6463 docs: mention "Allow commits from members who can merge..."
Mention the tick-box otherwise only the MR author can rebase the series.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reivewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-02-26 11:27:10 +00:00
Emil Velikov
d9d1cb43d7 egl/android: bump the number of drmDevices to 64
It's the current maximum supported by the kernel. Stay consistent with
the rest of Mesa and use the same number.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-26 11:07:23 +00:00
Emil Velikov
02344fe80b loader: use loader_open_device() to handle O_CLOEXEC
Some platforms lack O_CLOEXEC. The loader_open_device() handles those
appropriately, so use the helper.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 11:07:23 +00:00
Emil Velikov
f0a7b463b5 meson: egl: correctly manage loader/xmlconfig
Earlier commit introduced support for haiku yet did not properly
annotate the loader/xmlconfig dependencies.

Thus we ended up adding inc_loader for each !haiku platform - see
659910eda0 9a96bf0ecd c731508b98 ec6cb01e21.

One piece remained though - the wayland platform. Hence the following
would fail:

 meson -Dgallium-drivers=etnaviv -Ddri-drivers=''\
       -Dtools=etnaviv -Dplatforms=wayland -Dglx=disabled \
       build/

Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Reported-by: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 834d221512 ("meson: Add Haiku platform support v4")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-02-26 11:07:23 +00:00
Emil Velikov
9d84a922b8 egl/dri: de-duplicate dri2_load_driver*
The difference between the three functions is the list of mandatory
driver extensions. Pass that as an argument to the common helper.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-26 11:07:23 +00:00
Samuel Pitoiset
4924dfc851 radv: don't copy buffer descriptors list for samplers
Sampler descriptors don't have a buffer list.

This fixes some crashes with new CTS
dEQP-VK.binding_model.descriptor_copy.*.sampler_*.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-02-26 11:22:28 +01:00
Samuel Pitoiset
9256e0a09d radv: fix out-of-bounds access when copying descriptors BO list
We shouldn't increment the buffer list pointers twice.

This fixes some crashes with new CTS
dEQP-VK.binding_model.descriptor_copy.*.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-02-26 11:22:22 +01:00
Tapani Pälli
1d5e5ec30a nir: use nir_variable_create instead of open-coding the logic
Fixes: 3d7611e9 "st/nir: use NIR for asm programs"
Reported-by: Matthias Lorenz <oschowa@web.de>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-02-26 09:00:36 +02:00
Tapani Pälli
22267feff1 nir: initialize value in copy_prop_vars_block
Fixes following valgrind warning:

   ==27561== Conditional jump or move depends on uninitialised value(s)
   ==27561==    at 0x667856B: value_set_ssa_components (nir_opt_copy_prop_vars.c:78)
   ==27561==    by 0x667A1C4: copy_prop_vars_block (nir_opt_copy_prop_vars.c:797)

Fixes: 62332d139c "nir: Add a local variable-based copy propagation pass"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-02-26 08:56:25 +02:00
Eric Anholt
97566efe5c v3d: Rematerialize MOVs of uniforms instead of spilling them.
If we have a MOV of a uniform value available to spill, that's one of our
best choices.  We can just not spill the value, and emit a new load of the
uniform as the fill.  This saves bothering the TMU and the thrsw, and is
the same cost in uniforms (since the spill offset is a uniform anyway).

This doesn't have a huge impact on shader-db, since there aren't a whole
lot of spills and we usually copy-prop the uniforms at the VIR level such
that the only uniform MOVs are from vir_lower_uniforms:

total instructions in shared programs: 6430292 -> 6430279 (<.01%)
total uniforms in shared programs: 2386023 -> 2385787 (<.01%)
total spills in shared programs: 4961 -> 4960 (-0.02%)
total fills in shared programs: 6352 -> 6350 (-0.03%)

However, I'm interested in dropping the uniforms copy-prop in the backend,
since it would be cheaper to not load repeated uniforms if we have the
registers to spare.  This also saves many spills on
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20, which is what
motivated a bunch of my recent backend work in the first place:

before: 46 spills, 106 fills, 3062 instructions
after: 0 spills, 0 fills, 2611 instructions
2019-02-25 21:33:47 -08:00
Eric Anholt
e0fada983d v3d: Dump the VIR after register spilling if we were forced to.
Spilling is unusual, but one often has to debug it when it happens, so
dump it.
2019-02-25 21:26:24 -08:00
Eric Anholt
2786d2161a v3d: Fix vir_is_raw_mov() for input unpacks.
There are no users at the moment, but I wanted to start using this in
register spilling.
2019-02-25 21:26:24 -08:00
Mathias Fröhlich
1ab2159249 st/mesa: Reduce array updates due to current changes.
Since using bitmasks we can easily check if we have any
current value that is potentially uploaded on array setup.
So check for any potential vertex program input that is not
already a vao enabled array. Only flag array update if there is
a potential overlap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-02-26 05:42:04 +01:00
Dylan Baker
6f42303646 meson/iris: Use current coding style
Just a few minor style things.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-02-25 23:37:27 +00:00
Timothy Arceri
603206d0a6 radeonsi: fix query buffer allocation
Fix the logic for buffer full check on alloc.

This patch just takes the fix Nicolai attached to the bug report
and updates it to work on master.

Fixes: e0f0d3675d ("radeonsi: factor si_query_buffer logic out of si_query_hw")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109561
2019-02-26 09:55:41 +11:00
Eric Anholt
7c1bf075f3 nir: Just return when asked to rewrite uses of an SSA def to itself.
The nir_builder swizzling improvement to not emit extra MOVs resulted in
nir_lower_tex() trying to rewrite an SSA def to itself, triggering the
assert on all texturing in v3d.  There's no work to be done in this case,
so just stop asserting.

Fixes: 743700be1f ("nir/builder: Don't emit no-op swizzles")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-02-25 21:25:24 +00:00
Samuel Pitoiset
5671f38085 radv: fix clearing attachments in secondary command buffers
If no framebuffer is bound, get the number of samples and the
image format from the render pass.

This fixes new CTS dEQP-VK.geometry.layered.*.secondary_cmd_buffer.

Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-02-25 21:42:50 +01:00
Alok Hota
773b3ceaca swr/rast: Fix autotools and scons codegen
Use new input flags for gen_archrast.py

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-02-25 13:05:39 -06:00
Alok Hota
16e10b8c30 swr/rast: Add general SWTag statistics
Update Archrast parser to use stats, used with an internal tool

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-02-25 13:05:36 -06:00
Alok Hota
b45a15a39f swr/rast: Add string handling to AR event framework
For use by an internal tool

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-02-25 13:05:31 -06:00
Alok Hota
8608a747aa swr/rast: Add initial SWTag proto definitions
Update gen_archrast.py to properly generate event IDs

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-02-25 13:05:17 -06:00
Alok Hota
93cd9905c8 swr/rast: Cleanup and generalize gen_archrast
Update meson.build to accomodate

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2019-02-25 13:05:07 -06:00
Daniel Schürmann
0bd45f96b9 nir: Use SM5 properties to optimize shift(a@32, iand(31, b))
This is a common pattern from HLSL->SPIRV translation
and supported in HW by all current NIR backends.

vkpipeline-db results anv (SKL):

    total instructions in shared programs: 6403130 -> 6402380 (-0.01%)
    instructions in affected programs: 204084 -> 203334 (-0.37%)
    helped: 208
    HURT: 0

    total cycles in shared programs: 1915629582 -> 1918198408 (0.13%)
    cycles in affected programs: 1158892682 -> 1161461508 (0.22%)
    helped: 107
    HURT: 86

shader-db results on i965 (KBL):

    total instructions in shared programs: 15284592 -> 15284568 (<.01%)
    instructions in affected programs: 81683 -> 81659 (-0.03%)
    helped: 24
    HURT: 0

    total cycles in shared programs: 375013622 -> 375013932 (<.01%)
    cycles in affected programs: 40169618 -> 40169928 (<.01%)
    helped: 13
    HURT: 9

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-02-25 12:59:44 -06:00
Daniel Schürmann
0525bdc225 nir: Define shifts according to SM5 specification.
SPIR-V shifts are undefined for values >= bitsize, but SM5 shifts
are defined to only use the least significant bits.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-02-25 12:59:43 -06:00
Jason Ekstrand
c4fb6b0c81 intel/eu: Add an EOT parameter to send_indirect_[split]_message
For split indirect sends we have to put the EOT parameter in the
extended descriptor as well as the instruction itself so just calling
brw_inst_set_eot is insufficient.  Moving the EOT handling handling into
the send_indirect_[split]_message helper lets us handle it properly.
2019-02-25 11:35:12 -06:00
Sergii Romantsov
dcc4866419 d3d: meson: do not prefix user provided d3d-drivers-path
The user can select the location where there d3d drivers
are installed by the d3d-drivers-path meson option.

By default path will be $prefix/$libdir/d3d.

Currently we add $prefix to the user provided path.
Resulting in an incorrect or even missing path.

Based on logic of
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109698
CC: Kenneth Graunke <kenneth@whitecape.org>
CC: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-25 16:07:02 +00:00
Sergii Romantsov
f6556ec7d1 dri: meson: do not prefix user provided dri-drivers-path
The user can select the location where there dri drivers
are installed by the dri-drivers-path meson option.

By default path will be $prefix/$libdir/dri.

Currently we add $prefix to the user provided path.
Resulting in an incorrect or even missing path.

v2: fixed dri_search_path by default, rebased to master

v3: new commit-message (Emil Velikov), cc mesa-stable

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109698
CC: Rafael Antognolli <rafael.antognolli@intel.com>
CC: Dylan Baker <dylan@pnwbakers.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Fixes: 306914db92 (meson: Add dridriverdir variable to dri.pc.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-02-25 16:07:02 +00:00
Lionel Landwerlin
30828f4646 intel/aub_viewer: silence more compiler warnings
format not a string literal and no format arguments.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-25 13:11:16 +00:00
Lionel Landwerlin
91df8b1780 intel/aub_viewer: silence compiler warning
buffer_addr may be used uninitialized.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-25 13:11:13 +00:00
Lionel Landwerlin
f1da10e0c5 intel/aub_viewer: printout 48bits addresses
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-25 13:11:05 +00:00
Gert Wollny
875942c059 mesa/core: Enable EXT_depth_clamp for GLES >= 2.0
The extension NV_depth_clamp is written against OpenGL 1.2.1, and
since GLES 2.0 is based on GL 2.0 there is no reason not to enable
this extension also for GLES >= 2.0.

v2: Use EXT_depth_clamp that has been proposed to Khronos

v3: - Fix check for extension availability (Erik Faya-Lund)
    - Also fix the test in is_enabled
v4: - Test both, ARB and EXT extension (Erik)
v5: - Fix white space errors (Erik)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-02-25 09:44:27 +00:00
Kenneth Graunke
b45186a6cd iris: Properly allow rendering to RGBX formats.
I was converting them at pipe_surface creation time, but not when
answering queries about whether formats support rendering.  This caused
a lot of FBO incomplete errors for formats that ought to be supported.

Fixes "Child of Light", which uses PIPE_FORMAT_R8G8B8X8_UNORM_SRGB.

Also fixes Witcher 1 using wined3d (GL) according to Timur Kristóf.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109738
2019-02-25 01:11:27 -08:00
Kenneth Graunke
fce089c8a2 iris: Drop RGBX -> RGBA for storage image usages
GLSL doesn't expose RGB/RGBX image formats, so this isn't needed.
2019-02-25 00:57:50 -08:00
Kenneth Graunke
6921588d54 mesa: Fix RGBBuffers for renderbuffers with sized internal formats
For texture attachments, 'f' is texImg->_BaseFormat, but for
renderbuffer attachments, 'f' is att->Renderbuffer->InternalFormat.

InternalFormat may be something like GL_RGB8, which causes our
(f == GL_RGB) check to fail.  Switch to using a proper _BaseFormat,
which drops the size.

Fixes dEQP-GLES31.functional.draw_buffers_indexed.random.
max_required_draw_buffers.15 on iris when combined with a driver fix.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
2019-02-25 00:57:42 -08:00
Oscar Blumberg
da9c030763 glsl: Fix function return typechecking
apply_implicit_conversion only converts and check base types but we
need actual type equality for function returns, otherwise you can
return a vec2 from a function declared as returning a float.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-02-25 08:49:06 +02:00
Jordan Justen
bd0ad651e0 iris: Always use in-tree i915_drm.h
Ref: f1374805a8 "drm-uapi: use local files, not system libdrm"
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-02-24 21:06:40 -08:00
Alyssa Rosenzweig
f943047e48 panfrost: Decode render target swizzle/channels
On MRT-capable systems, the framebuffer format is encoded as a 64-bit
word in the render target descriptor. Previously, the two 32-bit
words were exposed as opaque hex values. This commit identifies a 12-bit
Mali swizzle and a 2-bit channel counter, removing some of the magic. It
also adds decoding support for the AFBC and MSAA enable bits, which were
already known but otherwise ignored in pandecode.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-02-25 04:49:50 +00:00
Alyssa Rosenzweig
c6be9969d2 panfrost/midgard: Add fround(_even), ftrunc, ffma
These ops were discovered by invoking the correspondingly names GLSL
functions. The rounding ops here behave exact as expected and are mapped
to their corresponding NIR ops where applicable. The ffma behaves as a
LUT instruction and requires some special argument packing (since
Midgard normally only allows for 2 arguments); this quirk will be
addressed in the future, but for now FMA is still lowered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-02-25 02:36:26 +00:00
Alyssa Rosenzweig
4a4726af3c panfrost/nondrm: Split out dump_counters
Previously, this function was implied a part of the job submit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-02-25 02:34:16 +00:00
Alyssa Rosenzweig
cdca103d43 panfrost/nondrm: Make COHERENT_LOCAL explicit
This flag corresponds to what was MEM_COHERENT_LOCAL in the vendor
driver, which seems to influence the cache policy, necessary for the
varying temporary storage but nothing else.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-02-25 02:32:45 +00:00
Alyssa Rosenzweig
f44d4653a9 panfrost/nondrm: Flag CPU-invisible regions
Potentially, the kernel could optimize these allocations, or perhaps we
can save on mapping costs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-02-25 02:31:09 +00:00