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Author SHA1 Message Date
Rhys Perry
fcf52eb42d aco: add check_vop3_operands() 
This will be useful when taking advantage of GFX10 features.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
cef7879719 aco: rewrite apply_sgprs() 
This will make it easier to apply two different sgprs (for GFX10) or apply
the same sgpr twice (just remove the break).

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
0be7409069 aco: rewrite literal combining 
Should make taking advantage of GFX10's increased constant bus limit and
VOP3 literals easier.

No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
84b9f3786b aco: improve can_use_VOP3() 
No pipeline-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
3cb98ed939 aco: combine two sgprs into a VALU if they're the same 
This was supposed to be done before but it wasn't done correctly and
everywhere.

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 784680 -> 786128 (0.18 %)
VGPRS: 574012 -> 573892 (-0.02 %)
Spilled SGPRs: 461 -> 461 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 45477088 -> 45478172 (0.00 %) bytes
Max Waves: 81294 -> 81277 (-0.02 %)
Instructions: 8657970 -> 8622483 (-0.41 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 780664 -> 782072 (0.18 %)
VGPRS: 573880 -> 573760 (-0.02 %)
Spilled SGPRs: 629 -> 629 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 45445244 -> 45448340 (0.01 %) bytes
Max Waves: 81178 -> 81161 (-0.02 %)
Instructions: 8649902 -> 8614918 (-0.40 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
c240c1aecf aco: apply literals to split mads 
Removing the return is also needed to apply literals to mads (which can be
done on GFX10).

pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 368787 -> 367555 (-0.33 %)
VGPRS: 312436 -> 312448 (0.00 %)
Spilled SGPRs: 461 -> 461 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 26113388 -> 26098260 (-0.06 %) bytes
Max Waves: 35982 -> 35982 (0.00 %)
Instructions: 5038670 -> 5028941 (-0.19 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 369843 -> 368659 (-0.32 %)
VGPRS: 317224 -> 317196 (-0.01 %)
Spilled SGPRs: 629 -> 629 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 26310540 -> 26295156 (-0.06 %) bytes
Max Waves: 36324 -> 36326 (0.01 %)
Instructions: 5073957 -> 5064164 (-0.19 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:28 +00:00
Rhys Perry
8f10e48745 aco: update IR validator 
GFX10 increased the constant bus limit and allowed literals on VOP3

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
 2020-01-14 12:56:27 +00:00
Rhys Perry
1ffacc3ce1 nir/lower_gs_intrinsics: add option for per-stream counts 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2422>
 2020-01-14 12:11:14 +00:00
Rhys Perry
9fb0c2e033 nir/divergence: handle load_primitive_id in GS 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2323>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2323>
 2020-01-14 11:29:44 +00:00
Erik Faye-Lund
9aab36b6eb mesa/st: use float literals 
This removes a warning on MSVC.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2020-01-14 12:01:29 +01:00
Erik Faye-Lund
fcdd3c866b gallium: fix a warning 
On some platforms (like Win64), unsigned long is 32-bit, so the first
cast doesn't do anything, and the compiler complains about an implicit
cast to a smaller type. So let's cast to an uintptr_t instead first,
as that's large enough on all platforms.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2020-01-14 12:01:05 +01:00
Erik Faye-Lund
1a1e5a763a st/wgl: eliminate implicit cast warning 
I get warnings on MSVC for these implicit casts. Let's use explicit
casts instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2020-01-14 12:01:00 +01:00
Erik Faye-Lund
d5c0fbfd78 util: initialize float-array with float-literals 
We currently initialize this float-array with double-literals. Some
compilers generate warnings for this, so let's switch these to
float-literals instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2020-01-14 12:00:27 +01:00
Lionel Landwerlin
b34422db5e anv: Implement Gen12 workaround for non pipelined state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
 2020-01-14 11:52:36 +02:00
Lionel Landwerlin
b8fbb39ab2 iris: Implement Gen12 workaround for non pipelined state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
 2020-01-14 11:52:36 +02:00
Vasily Khoruzhick
55b0aa436e lima: add new findings to texture descriptor 
Lower 8 bits of unknown_1_3 seems to be min_lod,
rest of 4 bits + miplevels are max_lod and min_mipfilter seems to be
lod bias. All are in fixed format with 4 bit integer and 4 bit fraction,
lod_bias also has sign bit.

Blob also seems to do some magic with lod_bias if min filter is nearest --
it adds 0.5 to lod_bias in this case. Same story when all filters are
nearest and mipmapping is enabled, but in this case it subtracts 1/16
from lod_bias.

Fixes 134 dEQP tests in dEQP-GLES2.functional.texture.*

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
 2020-01-13 22:50:36 -08:00
Kenneth Graunke
a9bd0668d5 intel: Use similar brand strings to the Windows drivers 
This updates our product name strings to match the ones reported
by the Windows driver, which is typically the marketing name.

We retain a platform abbreviation and GT level in parenthesis so that
we're able to distinguish similar parts more easily, helping us better
understand at a glance which GPU a bug reporter has.

Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
 2020-01-13 19:42:35 -08:00
Kenneth Graunke
f63d6260d1 iris: Simplify iris_get_renderer_string() 
We use gen_get_device_name() instead of PCI ID list munging.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
 2020-01-13 19:42:30 -08:00
Kenneth Graunke
44bad9c31a i965: Simplify brw_get_renderer_string() 
This stops using driGetRendererString() in favor of a simple snprintf().
This should have the same functionality on 64-bit systems, but drops
a "x86/MMX/SSE2" suffix on 32-bit systems.  (People shouldn't be using
the GL_RENDERER string to check for CPU features...)

We also use gen_get_device_name() instead of PCI ID list munging.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
 2020-01-13 19:42:22 -08:00
Kenneth Graunke
50c47ba49e Revert "nir: assert that nir_lower_tex runs after lowering derefs" 
This reverts commit 4cda61f11e for now,
as it appears to break i965 CI (32,000+ failures).  Rob and I suspect
we need to do the equivalent of 1c6a2efa06
on i965 - we are doing nir_lower_tex and brw_nir_lower_resources in the
wrong order and that's likely triggering this condition.  Once we fix
that, we should put this patch back.
 2020-01-13 17:37:40 -08:00
Erik Faye-Lund
09b37ba65f zink: fixup initialization of operand_mask / num_extra_operands 
This doesn't change behavior, but makes the code a bit easier to read.
Both values are zero, but I somehow swapped the logical meaning of them
when initializing.
 2020-01-14 01:06:59 +00:00
Eric Anholt
3be4b89c03 mesa: Fix detection of invalidating both depth and stencil. 
Fixes an extra 1024x1024x4 MSAA Z/S store on WebGL fishtank on cheza.

Reported-by: Dave Airlie <airlied@redhat.com>
Fixes: db2ae51121 ("mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3370>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3370>
 2020-01-13 23:37:54 +00:00
Rob Clark
1c6a2efa06 mesa/st: lower samplers before nir_lower_tex 
Fixes incorrect lowering of YUV samplers when there are non-yuv
samplers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
 2020-01-13 23:19:49 +00:00
Rob Clark
4cda61f11e nir: assert that nir_lower_tex runs after lowering derefs 
It isn't going to do the right thing, because texture_index/
sampler_index defaults to zero.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3368>
 2020-01-13 23:19:49 +00:00
Gurchetan Singh
d72f178753 i965: support EXT_EGL_image_storage 
i965 can support this.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:36 -08:00
Gurchetan Singh
b1c266d5fa i965: refactor intel_image_target_texture_2d 
intel_image_target_texture_tex_storage can reuse much of this
code.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:32 -08:00
Gurchetan Singh
34fe560cd6 i965: track if image is created by a dmabuf 
Will be used by EXT_EGL_image_storage later.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:27 -08:00
Gurchetan Singh
bf576772ab dri_util: add driImageFormatToSizedInternalGLFormat function 
This is needed to implement the EXT_EGL_image_storage spec:

"If <target> is GL_TEXTURE_2D, then the resultant texture must have a
sized internal format which is colorspace and size compatible with the
dma-buf.  If the GL is unable to determine such a format, the error
INVALID_OPERATION is generated."

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:22 -08:00
Gurchetan Singh
b68ff2b873 glapi / teximage: implement EGLImageTargetTexStorageEXT 
Check various parts of the EXT_EGL_image_storage spec, and add a
new vfunc for drivers implementing it.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:18 -08:00
Gurchetan Singh
1fe23d0e22 teximage: split out helper from EGLImageTargetTexture2DOES 
The major differences between EXT_EGL_image_storage and
EGLImageTargetTexture2DOES are:

(1) The texture target is made immutable
(2) EXT_EGL_image_storage supports non-2D targets.

We can reuse EGLImageTargetTexture2D and FreeTextureImageBuffer
for (1) pretty easily.  For (2), let's just not support the
complicated targets.  Let's reuse aspects of the
EGLImageTargetTexture2DOES implementation.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-13 14:57:07 -08:00
Jason Ekstrand
7978f2401b anv: Memset array properties 
This is probably better than possibly leaving those bytes uninitialized
even if the app will theoretically not use them.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
 2020-01-13 22:33:55 +00:00
Jason Ekstrand
d36eed3e69 anv: Don't over-advertise descriptor indexing features 
We should only advertise sub-features if we advertise the extension.

Fixes: 6e230d7607 "anv: Implement VK_EXT_descriptor_indexing"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3369>
 2020-01-13 22:33:55 +00:00
Jason Ekstrand
d7ff137445 intel/blorp: Fill out all the dwords of MI_ATOMIC 
This makes us valgrind clean again.

Fixes: 9175c7058e "intel/blorp: Make blorp update the clear color..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
 2020-01-13 21:48:00 +00:00
Tomeu Vizoso
40dd418e14 gitlab-ci: Upgrade kernel for LAVA jobs to v5.5-rc5 
Some fixes got in that should prevent hangs in lima jobs.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3363>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3363>
 2020-01-13 21:26:11 +00:00
Daniel Schürmann
05c81875d7 aco: fix unconditional demote_to_helper 
This patch fixes an out-of-bounds access on p_exit_early
and binds the exec register to the correct operand.

Fixes: 2ea9e59e8d ('aco: move s_andn2_b64 instructions out of the p_discard_if')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3347>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3347>
 2020-01-13 21:08:41 +00:00
Marek Olšák
2bb88b2fdc radeonsi: don't enable VBOs in user SGPRs if compute-based culling can be used 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
363b4027fc radeonsi: put up to 5 VBO descriptors into user SGPRs 
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs

We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.

Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
220d00314f ac,radeonsi: increase the maximum number of shader args and return values 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
ef253c6789 radeonsi: simplify si_set_vertex_buffers 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
312e04689a radeonsi: don't allow draw calls with uninitialized VS inputs 
These always hang, because vertex buffer descriptors are not set up.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
c278c73f13 radeonsi: add si_context::num_vertex_elements 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
1e03b63b3b radeonsi: rename desc_list_byte_size -> vb_desc_list_alloc_size 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Lionel Landwerlin
2cc14bd7b8 anv: set stencil layout for input attachments 
If an input attachment has a stencil format, we need to set this.

v2: Fish out VkAttachmentReferenceStencilLayoutKHR from
    VkAttachmentReference2KHR::pNext (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: c1c346f166 ("anv: implement VK_KHR_separate_depth_stencil_layouts")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2891>
 2020-01-13 21:57:33 +02:00
Jason Ekstrand
21bc16a723 anv: Drop an unused variable 2020-01-13 12:20:48 -06:00
Jason Ekstrand
d3737002ee nir/lower_atomics_to_ssbo: Also lower barriers 
This is more correct for a pass which is supposed to completely lower
away atomic counters.  It also lets us stop supporting atomic counter
barriers in most of the drivers.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00
Jason Ekstrand
e40b11bbcb nir: Rename nir_intrinsic_barrier to control_barrier 
This is a more explicit name now that we don't want it to be doing any
memory barrier stuff for us.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00
Jason Ekstrand
bd3ab75aef intel/nir: Stop adding redundant barriers 
Now that both GLSL and SPIR-V are adding shared and tcs_patch barriers
(as appropreate) prior to the nir_intrinsic_barrier, we don't need to do
it ourselves in the back-end.  This reverts commit
26e950a5de01564e3b5f2148ae994454ae5205fe.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00
Jason Ekstrand
ba43b66dc9 nir/glsl: Emit memory barriers as part of barrier() 
The GLSL barrier() intrinsic does an implicit shared memory barrier in
compute shaders and an implicit TCS patch output barrier in tessellation
control shaders.  We'd like NIR's barrier intrinsic to just be a control
flow barrier and not have memory implications.  To satisfy this, we need
to add an extra memory barrier in front of each nir_intrinsic_barrier.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00
Jason Ekstrand
a4125b4d26 spirv: Add output memory semantics to OpControlBarrier in TCS 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00
Jason Ekstrand
2365520c9d spirv: Add a workaround for OpControlBarrier on old GLSLang 
As per the Vulkan memory model, the proper translation of GLSL barrier()
is an OpControlBarrier with a scope of Workgroup and semantics of
Acquire, Release, and WorkgroupMemory.  Older versions of GLSLang gave
an OpControlBarrier with semantics of None so we need to patch it up on
those versions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
 2020-01-13 17:23:47 +00:00