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Author SHA1 Message Date
Alyssa Rosenzweig
b4d8be165b asahi: Implement ARB_texture_mirror_clamp_to_edge 
Guessing the enum value, passes texwrap piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>
 2023-01-09 23:58:52 +00:00
Alyssa Rosenzweig
0e2d786579 asahi: Implement GL_CLAMP natively 
Turns out there's a hardware mode for this. Apple's GL driver uses this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>
 2023-01-09 23:58:52 +00:00
Lionel Landwerlin
8679956e63 ci/zink+anv: remove dEQP-GLES31.functional.layout_binding.ubo.* 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>
 2023-01-09 23:00:24 +00:00
Lionel Landwerlin
2d627f28c8 anv: use the null surface with unused push descriptor binding table entries 
Some binding table entries have been identify as unused in the shaders
by the push constant analysis pass. We can just put the null entry in
there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0b7 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>
 2023-01-09 23:00:24 +00:00
Lionel Landwerlin
bbfca4eb92 anv: return properly typed value for no ubo promoted 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>
 2023-01-09 23:00:24 +00:00
Lionel Landwerlin
e2b0086b78 anv: check that push range actually match binding considered 
We can't just check the load_ubo range is contained in the push entry,
we also need to check that the push entry set/binding matches the
load_ubo set/binding.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>
 2023-01-09 23:00:24 +00:00
Lionel Landwerlin
48bb3df951 anv: don't nullify entries 
We'll use those to fill the push constant addresses, so we can't have
them turned to null.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>
 2023-01-09 23:00:24 +00:00
Tapani Pälli
319d485679 iris: let isl set tiling mode for external resources 
Patch sets memory object external format (which is otherwise
PIPE_FORMAT_NONE for memory objects) before main surface gets
configured. With this we can add a check that when dealing
with external resource that has no modifier set, we let isl
figure out the tiling mode.

Fixes memobj tests on DG2:
   piglit.spec.ext_external_objects.vk-image-display-muliple-textures
   piglit.spec.ext_external_objects.vk-image-display-overwrite
   piglit.spec.ext_external_objects.vk-depth-display
   piglit.spec.ext_external_objects.vk-image-display
   piglit.spec.ext_external_objects.vk-stencil-display

v2: add assert and comment on tiling decision (Ken)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7684
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20473>
 2023-01-09 22:38:29 +00:00
Rhys Perry
fdf4a87823 radv/rt: use a smaller value to enable scratch 
The scratch allocation alignment on GFX11 is small enough that this should
help. Would be nice to someday remove this hack completely though.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>
 2023-01-09 21:46:13 +00:00
Rhys Perry
810ced93f3 aco: align scratch size during assembly 
This lets us use less scratch if both VGPR spilling and scratch intrinsics
are used.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>
 2023-01-09 21:46:13 +00:00
Rhys Perry
c9846158cd aco/gfx11: reduce scratch allocation alignment 
fossil-db (gfx1100):
Totals from 112 (0.08% of 134574) affected shaders:
Scratch: 1513472 -> 1455360 (-3.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>
 2023-01-09 21:46:13 +00:00
Qiu Wenbo
ee32f3873c vc4: Fix running process_mux_deps on irrelevant type of instructions 
Only ALU and ALU Small Imm instructions have input mux.

Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>
 2023-01-09 20:22:47 +00:00
Qiu Wenbo
7489c29abe vc4: Fix RADDR_A field extraction of branch instruction 
Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>
 2023-01-09 20:22:47 +00:00
Mike Blumenkrantz
82bd38fa11 zink: add a bunch of asserts for starting dynamic render 
try to avoid any race condition bugs triggering later when they're
harder to catch

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Mike Blumenkrantz
0997a6272e zink: re-clamp dynamic render area when doing swapchain fixups 
this may catch another corner case if a late fixup changes fb size

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.clear_render

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Mike Blumenkrantz
c53fc5f48e zink: catch a potential corner case with dynamic render and swapchain updates 
zink_prep_fb_attachment() calls acquire internally, which means it's theoretically
possible that fixups are required very late in this function

never seen it happen, but who knows

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Mike Blumenkrantz
a59dc9d157 zink: split out swapchain render update fixups into separate function 
this needs to be more granular for corner cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Mike Blumenkrantz
6f02fe8842 zink: protect against invalid scissored renderpass clears 
if the clear region is oob, this is illegal and may crash some drivers

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_clear_render
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_render_clear

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Mike Blumenkrantz
79a4d22928 zink: only update framebuffer object during swapchain update if framebuffer exists 
otherwise this might be randomly creating an unused framebuffer for dynamic render

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>
 2023-01-09 20:06:14 +00:00
Ian Romanick
51be623372 intel/eu/validate: Check predication and cmod for SEL, CMP, and CMPN 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
e0f409c5d8 intel/eu/validate: Add validation for csel 
v2: Also check the condition modifier. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
3a7c23973b intel/eu/validate: Add validation for bfi2 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
f34821d998 intel/eu/validate: More validation for logic ops 
v2: Use number of source to condition validating src1 instead of using
the opcode. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
8be7406c81 intel/compiler: Assert that ARF used is the accumulator 
v2: Move the new check to be with similar existing checks. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
3b579a2ea8 intel/compiler: Validate 3-source instruction source strides 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick
c5684019f6 intel/compiler: Validate 3-source instruction sources have same base type 
This can't be checked in EU validation because the bits to describe the
base type of the individual sources no longer exist.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Georg Lehmann
c241980751 aco: Mark more instructions as 16bit on GFX10. 
p_cvt_f16_f32_rtne will be lowered to v_cvt_f16_f32 and we already know that
preserves the high bits.

I tested the others on GFX1036.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20574>
 2023-01-09 18:54:35 +00:00
Rhys Perry
b64afc1d37 aco: use s_delay_alu skip field 
fossil-db (gfx1100):
Totals from 130066 (96.65% of 134574) affected shaders:
Instrs: 80208817 -> 71420648 (-10.96%)
CodeSize: 403523036 -> 368370360 (-8.71%)
Latency: 658064779 -> 657935384 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 87698268 -> 87693326 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>
 2023-01-09 18:22:59 +00:00
Rhys Perry
e2f083c0a7 aco: add more dependency instructions under waitcnt class 
This makes these instructions free when considering pipeline statistics
and s_delay_alu insertion.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>
 2023-01-09 18:22:59 +00:00
Rhys Perry
c8357136d4 aco: improve parse_delay_alu 
Use gpr_map to determine how many cycles each dependency of the
s_delay_alu needs. This information helps the pass avoid further
s_delay_alu instructions.

fossil-db (gfx1100):
Totals from 13097 (9.73% of 134574) affected shaders:
Instrs: 30711894 -> 30702692 (-0.03%)
CodeSize: 153462500 -> 153425692 (-0.02%)
Latency: 372758612 -> 372741922 (-0.00%)
InvThroughput: 50164111 -> 50160717 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>
 2023-01-09 18:22:59 +00:00
Samuel Pitoiset
bbad550f3d radv/winsys: fill real info for CHIP_GFX1100 
From my AMD Radeon 7900 XT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20476>
 2023-01-09 17:28:05 +00:00
Samuel Pitoiset
d944959fbf radv: configure VGT_TF_PARAM directly from the command buffer 
The driver re-emits the tessellation domain origin state when a new
pipeline with tessellation is bound, so this can be moved there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>
 2023-01-09 15:46:49 +00:00
Samuel Pitoiset
f1b3e6aefd radv: fix re-emitting tessellation domain origin when it's dynamic 
The winding order can be different between pipelines.

Fixes new dEQP-VK.pipeline.pipeline_library.dynamic_control_points.change_*_winding.

Fixes: f22290949d ("radv: add support for dynamic tessellation domain origin")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>
 2023-01-09 15:46:49 +00:00
Pierre-Eric Pelloux-Prayer
6e24b76c10 util/00-mesa-defaults: add Limbo workaround 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7976
Cc: mesa-stable

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20548>
 2023-01-09 15:17:34 +00:00
José Roberto de Souza
1067ec90a5 anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+ 
This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

As no ANV_PIPE_INVALIDATE_BITS is set as parameter of
anv_add_pending_pipe_bits(),
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one
PIPELINE_CONTROL.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>
 2023-01-09 14:40:26 +00:00
José Roberto de Souza
172e0b0ebf iris: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+ 
This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>
 2023-01-09 14:40:26 +00:00
Pierre-Eric Pelloux-Prayer
595079c37c hud: extract float printf modifer selection logic to helper 
And use it when printing to a file from hud_graph_add_value.

This turns:
  fps: 59.972473
Into:
  fps: 59.97

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>
 2023-01-09 14:25:55 +01:00
Pierre-Eric Pelloux-Prayer
31d95dd3c6 dri: get rid of LIBGL_SHOW_FPS 
The same functionnality can be achieved using GALLIUM_HUD=stdout,fps (and for
now a fallback is doing this if LIBGL_SHOW_FPS=1 is used).

This removes one entry from the vtable and simplify dri3_handle_present_event.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>
 2023-01-09 14:25:51 +01:00
Pierre-Eric Pelloux-Prayer
87f4d79427 hud,dri: emulate LIBGL_SHOW_FPS using hud 
LIBGL_SHOW_FPS=1 is now almost equivalent to using:

   GALLIUM_HUD=stdout,fps
   GALLIUM_HUD_VISIBLE=false
   GALLIUM_HUD_PERIOD=$LIBGL_SHOW_FPS

so we can drop LIBGL_SHOW_FPS handling in dri and move it to hud.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>
 2023-01-09 14:25:43 +01:00
Pierre-Eric Pelloux-Prayer
0a3e91b9ee hud: add "stdout" option to print values to console 
Values gathered by the hud context will be printed to stdout,
prefixed by their name.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>
 2023-01-09 14:25:41 +01:00
Pierre-Eric Pelloux-Prayer
3170f7d7fa hud: check GALLIUM_HUD_DUMP_DIR value only once 
Minor cleanup but will allow another change in the next commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>
 2023-01-09 14:25:25 +01:00
Dmitry Osipenko
32fe60e8c4 util/disk_cache: Support combined foz ro and non-foz rw caches 
Mesa utilizes only one type of cache at a time. This patch enables support
for combined reading from read-only Fossilize cache + non-foz read-write
caches.

From now on, a non-foz read-write caches will first try to retrieve data
from a read-only foz cache if new MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ
environment variable is set to true, otherwise the caching behaviour is
unchanged. The new flag has no effect when MESA_DISK_CACHE_SINGLE_FILE=1,
i.e. when the single-file foz cache is used.

This change allows us to ship a prebuilt RO caches for a certain
applications, while the rest of applications will benefit from the
regular RW caching that supports cache-size limitation. This feature
will be used by ChromeOS.

Usage example #1:

MESA_DISK_CACHE_DATABASE=0
MESA_DISK_CACHE_SINGLE_FILE=0
MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ=1
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS=rocache1,rocache2

Usage example #2:

MESA_DISK_CACHE_DATABASE=1
MESA_DISK_CACHE_SINGLE_FILE=0
MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ=1
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS=rocache1,rocache2

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>
 2023-01-09 12:12:55 +00:00
Dmitry Osipenko
75dae4f8e3 util/disk_cache: Store environment variable values in disk_cache struct 
Store values of all environment variables related to disk caching within
struct disk_cache. This makes code cleaner and also will allow us to
combine read-only single-file cache with read-write caches.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>
 2023-01-09 12:12:55 +00:00
Dmitry Osipenko
434bf4b482 util/fossilize_db: Fix resource leaks in foz_prepare() error paths 
The foz_prepare() doesn't perform cleanup on failure and then foz_destroy()
is never invoked for the foz_db, causing minor memory and FD leaks. Add the
cleanup to foz_prepare() error code paths. Make foz_destroy() to clear the
foz_db struct for consistency, right now the destroying is invoked only once,
but Mesa cache error code paths aren't trivial and may change in the future.

Suggested-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>
 2023-01-09 12:12:55 +00:00
SoroushIMG
2b77a65800 zink: fix disappearing smooth lines after workaround 
The passthrough geometery shader was using points for smooth lines.
This meant the shader would always statically get 1 vertex and never emit a line.

Fixes: 80285db9ef ("zink: lower smooth-lines if not supported")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20582>
 2023-01-09 10:56:52 +00:00
Xaver Hugl
41eb491fb6 driconf: add a workaround for plasmashell freezing 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7624

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dan Johansen <strit@manjaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20472>
 2023-01-09 09:04:25 +00:00
Lionel Landwerlin
6b494745be intel/fs: only avoid SIMD32 if strictly inferior in throughput 
This enabled SIMD32 in blorp shaders and seems to be give a small FPS
bump when using a DG2 GPU as secondary (requires copies to linear
buffers to exchange with main GPU).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19341>
 2023-01-09 08:41:47 +00:00
Samuel Pitoiset
480308c6e5 radv: remove unused radv_is_raster_enabled() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>
 2023-01-09 08:20:10 +00:00
Samuel Pitoiset
1099fd71b0 radv: initialize blend state after compiling shaders 
This function used to compute part of the graphics key but everything
has been moved.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>
 2023-01-09 08:20:10 +00:00
Samuel Pitoiset
87b88de973 radv: replace blend_enable_4bit by radv_pipeline_is_blend_enabled() 
Same logic, though this workaround shouldn't be determined from the
pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>
 2023-01-09 08:20:10 +00:00