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Author SHA1 Message Date
Jesse Natalie
e8ab5e4320 d3d12: Use GetResourceAllocationInfo instead of GetCopyableFootprints for residency sizes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29967>
 2024-06-28 17:21:52 +00:00
José Expósito
1ef3b38ff8 llvmpipe: Init eglQueryDmaBufModifiersEXT num_modifiers 
Initialize the number of modifiers when `max` is 0 as documented [1]:

  If <max_formats> is 0, no formats are returned, but the total number
  of formats is returned in <num_formats>, and no error is generated.

[1] https://registry.khronos.org/EGL/extensions/EXT/EGL_EXT_image_dma_buf_import_modifiers.txt

Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Reported-by: Michal Odehnal <modehnal@redhat.com>
Tested-by: Michal Odehnal <modehnal@redhat.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Signed-off-by: José Expósito <jexposit@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29941>
 2024-06-28 16:57:26 +00:00
Caio Oliveira
6dc7f65a39 anv: Use brw_nir_lower_cs_intrinsics for lowering Mesh/Task LocalID 
Stop using the option in the generic pass
nir_lower_compute_system_values and use the same code as brw uses for
compute instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29828>
 2024-06-28 16:30:38 +00:00
Caio Oliveira
d89bfb1ff7 intel/brw: Reorganize lowering of LocalID/Index to handle Mesh/Task 
Reorganize the code to make clearer all the lowering cases:

(a) Single invocation workgroup.  Index and IDs are all zero.
(b) Local ID provided by hardware.
(c) Local Index provided by the hardware.  Depending on the case this
    might not be the final local index, e.g. heuristics for tile.
(d) Neither provided by the hardware.

Case (c) is new and supported by Mesh/Task shaders.  At the moment the
nir_lower_compute_system_values handle lowering of LocalID for
Task/Mesh, but a later patch will flip that on ANV.

This will make the Task/Mesh use the same lowering as Compute shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29828>
 2024-06-28 16:30:38 +00:00
Juan A. Suarez Romero
f0b0a71a9b ci: disable Igalia farm 
We have some network issues which prevents the hosts do their job

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29965>
 2024-06-28 16:27:17 +00:00
Connor Abbott
81fd13913a freedreno: Fix RBBM_NC_MODE_CNTL variants 
It exists on a6xx too, as made clear by kgsl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29961>
 2024-06-28 15:09:04 +00:00
Samuel Pitoiset
cc48e12431 radv: suspend user conditional rendering when DGC has task shaders 
Otherwise the DGC ACE IB would be uninitialized and it would hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29954>
 2024-06-28 14:35:22 +00:00
David Rosca
49eda4d742 frontends/va: Don't require exact match for packed headers 
Apparently it's valid to create config with any combination of supported
packed headers.

Fixes libva-utils tests:
 GetCreateConfig/VAAPIGetCreateConfig.CreateConfigWithAttributes/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 GetCreateConfig/VAAPIGetCreateConfig.CreateConfigPackedHeaders/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 QuerySurfaces/VAAPIQuerySurfaces.QuerySurfacesWithConfigAttribs/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 CreateSurfaces/VAAPICreateSurfaces.CreateSurfacesWithConfigAttribs/3995, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice, 16x16)

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29934>
 2024-06-28 14:19:22 +00:00
David Rosca
a3f35964ba gallium/vl: Init shaders on first use 
It takes significant amount of time at va context creation, and most
of the time the postproc pipelines are not used anyway.
This reduces total time it takes to run all libva-utils tests on my machine
from 38s to 28s.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29936>
 2024-06-28 13:34:35 +00:00
Luc Ma
6f1dd9a2aa gallium: inline trivial needs_pack() 
No functional change.

Signed-off-by: Luc Ma <luc@sietium.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29833>
 2024-06-28 11:22:23 +00:00
Luc Ma
cde1a1d5c2 gallium: properly propagate the usage of resource 
In case that some drivers might make decision depending on it,
it is better to tell drivers about usage of resource just like
in `blit_to_staging()` and `st_TexSubImage()` etc before going
to blit.

Signed-off-by: Luc Ma <luc@sietium.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29833>
 2024-06-28 11:22:23 +00:00
Konstantin Seurer
9ae1c5dce3 radv: Refactor radv_(dst|src)_access_flush 
A few ifs should be faster and more readable than looping over every set
bit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
41619da397 radv: Handle AS access bits like shader storage access bits 
Acceleration structures are accessed directly from shaders or via
PKT3_WRITE_DATA.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
ca96abe1cb radv: Remove write access handling from radv_dst_access_flush 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3eefd0b040 radv: Remove handling for expanded access flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
135348a3c3 radv: Remove no-op access flag handling 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3acab3dfff radv: Use vk_expand_(src|dst)_access_flags2 
Simplifies access flags handling since the driver doesn't have to worry
about VK_ACCESS_2_MEMORY_READ_BIT and friends.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
b0fa138c86 vulkan: Add vk_expand_(dst|src)_access_flags2 
Those helpers do not filter out dead access bits to keep synchronization
conservative.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
7b3cdacf7f vulkan: Handle group stages in vk_.*_access2_for_pipeline_stage_flags2 
Avoids calling vk_expand_.*_stage_flags2.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Eric Engestrom
76db69047f panfrost/ci: split gl & vk jobs rules 
No need to run all the gl jobs on vk changes, and vice-versa.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29942>
 2024-06-28 08:19:07 +00:00
Eric Engestrom
cdc0e60df5 panfrost/ci: drop duplicate job rules 
It's overwritten by the `.panfrost-bifrost-manual-rules` 3 lines below.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29942>
 2024-06-28 08:19:07 +00:00
Samuel Pitoiset
88864b707a radv: enable task shaders support with NV DGC 
No games are using task shaders with DGC at the moment but this is
supposed to work.

This fixes test_amplification_shader_execute_indirect from vkd3d.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
e6aee84265 radv: fix a synchronization issue with non-preprocessed DGC with task shader 
We need to make sure that the DGC ACE IB will wait for the DGC
prepare shader before the execution starts. When DGC is preprocessed
the synchronization is already correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
74713469e1 radv: disable conditional rendering with DGC and task shaders 
When the DGC prepare shader is conditionally executed on the graphics
queue, the generated IBs might be uninitialized. It's fine for the
DGC GFX IB because the INDIRECT_PACKET would also be conditionally
skipped but it's not possible to do that for the DGC ACE IB
(ie. no IB2 on compute).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
fec2385301 radv: emit push constant for task shaders with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1ffb420edd radv: adjust the base upload offset when DGC uses task shaders 
The upload space is after the DGC ACE IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f55d4f2f09 radv: reserve space for push constants in the DGC ACE IB 
The upload space will be shared for both IBs when push constants need
to be allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
8d321421c7 radv: rework emitting push constants with DGC 
Using a push constant stages mask to emit them in the DGC ACE IB for
task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f6150edbb3 radv: split allocating and emitting push constants with DGC 
This will allow us to emit push constants for task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1f7bdcfa8d radv: add a helper that determines if DGC uses task shaders 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
58327fd3bf radv: pre-compute the base upload offset in radv_prepare_dgc() 
It will need to be adjusted if task+mesh shaders need to allocate
push constants.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
842f3ea133 radv: improve clarity of DGC offset computations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
bc52e77397 radv: fix incorrect cache flushes before decompressing DCC on compute 
Found by luck.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29940>
 2024-06-28 05:54:20 +00:00
Sagar Ghuge
edcad250ed intel/compiler: Don't use half float param for sample_b 
Looks like some of the tests uses the bias which does not fit into half
float parameter, so it's better to use float param for sample_b.

If we have cube arrays, we anyway combine BIAS and array index properly
so we don't have to worry about the first parameter.

This fixes: GTF-GL46.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_clamp_m_g_M

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29533>
 2024-06-28 03:33:18 +00:00
Sushma Venkatesh Reddy
d8c2930da0 drm-uapi: Sync i915_drm.h with a78313bb206e 
Sync i915_drm.h with a78313bb206e
commit a78313bb206e0c456a989f380c4cbd8af8af7c76
Author: Dave Airlie <airlied@redhat.com>
Date:   Thu Jun 27 17:21:43 2024 +1000

    Merge tag 'drm-intel-gt-next-2024-06-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Fixes: a9f1151de2 ("intel/hang_replay: use hw image param")

Signed-off-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29885>
 2024-06-28 00:03:39 +00:00
Dylan Baker
35298e84f1 intel/compiler: move predicated_break out of backend loop 
This has no impact on the generated shaders, but does have a small
(positive) impact on the amount of time spent in shader compilation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29126>
 2024-06-27 15:20:19 -07:00
Jordan Justen
7b3149c99b intel/brw: Retype some regs to BRW_TYPE_UD for Xe2 indirect accesses 
Following https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957,
some Xe2 code paths started triggering asserts.

In the cases fixed by this patch, it was because of the assert added
to brw_type_larger_of() in cf8ed9925f ("intel/brw: Make a helper for
finding the largest of two types"), and then brw_type_larger_of() is
used in 674e89953f. (For example, the assert was triggering when the
SHL types differed between D and UD.)

Fixes: 674e89953f ("intel/brw: Use new builder helpers that allocate a VGRF destination")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29925>
 2024-06-27 21:51:07 +00:00
Karol Herbst
646a0ea576 meson: rename with_gallium_opencl to with_gallium_clover 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29646>
 2024-06-27 20:50:32 +00:00
Patrick Lerda
82e9880b04 clover: fix meson opencl-spirv option 
As reported by https://gitlab.freedesktop.org/mesa/mesa/-/issues/10674
this option is broken. Indeed, when "with_clc" is false the compilation
process failed with the following error:
"ERROR: Unknown variable "idep_mesaclc".

Fixes: 815a6647eb ("meson: do not pull in clc for clover")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10674
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29646>
 2024-06-27 20:50:32 +00:00
Paulo Zanoni
746f41e705 anv: properly store the engine_class_supported_count values 
Function anv_physical_device_try_create() creates the devinfo variable
and then at some point it copies its contents to device->info:

  device->info = devinfo;

Much much later we're calling:

  intel_common_update_device_info(fd, &devinfo);

... which is updating devinfo but not device->info. As a consequence,
we're only creating one queue, as engine_class_supported_count[klass]
is zero for everybody.

Fixes: 5b8b4f7878 ("intel/dev: Add engine_class_supported_count to intel_device_info")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29927>
 2024-06-27 20:19:39 +00:00
Lionel Landwerlin
cff6df7e11 anv: limit vertex fetch invalidation on indirect read 
Only used on Gfx9

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29810>
 2024-06-27 19:01:50 +00:00
Ian Romanick
531461d576 intel/brw: Test corner case CSE of ADD3 instructions 
When the destination of both instructions is NULL and the conditional
modifier matches, operands_match (by way of instructions_match) will
only test the first two operands. This can result in bad CSE
happening.

This is a very, very narrow edge case.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29848>
 2024-06-27 18:34:53 +00:00
Kenneth Graunke
7adccbd48d intel/brw: Support CSE of ADD3 
This one is a bit more complex in that we need to handle 3-source
commutative opcodes.  But it's also quite useful:

fossil-db results on Alchemist (A770):

    Instrs: 151659750 -> 150164959 (-0.99%); split: -0.99%, +0.01%
    Cycles: 12822686329 -> 12574996669 (-1.93%); split: -2.05%, +0.12%
    Subgroup size: 7589608 -> 7589592 (-0.00%)
    Send messages: 7375047 -> 7375053 (+0.00%); split: -0.00%, +0.00%
    Loop count: 46313 -> 46315 (+0.00%); split: -0.01%, +0.01%
    Spill count: 110184 -> 54670 (-50.38%); split: -50.79%, +0.41%
    Fill count: 213724 -> 104802 (-50.96%); split: -51.43%, +0.47%
    Scratch Memory Size: 9406464 -> 3375104 (-64.12%); split: -64.35%, +0.23%

Our older Shadow of the Tomb Raider fossil is particularly helped with
over a 90% reduction in scratch access (spills, fills, and scratch
size).  However, benchmarking in the actual game shows no change in
performance.  We're thinking the game's shaders have been updated since
our capture.

Ian noted that there was a bug here where we'd accidentally CSE two ADD3
instructions with null destinations and different src[2] that couldn't
be dead code eliminated due to conditional mods.  However, this is only
a bug in the new cse_defs pass so we don't need to nominate this for
stable branches.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29848>
 2024-06-27 18:34:53 +00:00
Eric Engestrom
e1b1114bc2 v3d/ci: add nightly job for rusticl testing 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:02 +00:00
Eric Engestrom
959d38099f llvmpipe,rusticl/ci: move rusticl files rule out of llvmpipe 
With the next commit, llvmpipe will no longer be the only driver to test rusticl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:02 +00:00
Eric Engestrom
70dfe9c6d1 ci: include rusticl in the arm64 build 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:02 +00:00
Eric Engestrom
b2a025f9a2 llvmpipe/ci: set rusticl variables in deqp-runner instead of passing them down from the job 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:02 +00:00
Eric Engestrom
5b3782a5ab llvmpipe/ci: fix indentation of list nested in a dict item 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:01 +00:00
Eric Engestrom
3d09f93287 llvmpipe/ci: add comment for later on weird-looking code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29851>
 2024-06-27 17:49:01 +00:00
Mike Blumenkrantz
332252966b ci: kill filament trace globally 
this one is flaky and pointless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29937>
 2024-06-27 14:36:13 +00:00