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Author SHA1 Message Date
Alyssa Rosenzweig
f8151312af pan/bi: Add data register passing infrastructure 
Lower to a COMBINE, which in turn will lower to moves so RA does the
right thing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:15 -04:00
Alyssa Rosenzweig
3bf4e60def pan/bi: Stub out TEXC handling 
We still need to handle actual complex texturing instructions, as well
as packing, but this is the start.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:15 -04:00
Alyssa Rosenzweig
dcce3feb79 pan/bi: Add texture operator descriptor 
Used to encode all the different texture modes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:14 -04:00
Alyssa Rosenzweig
d99df25d5d pan/bi: Pack skip bit for texture operations 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:14 -04:00
Alyssa Rosenzweig
39ec3eb6e7 pan/bi: Encode skip bit into IR 
Currently unset.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:14 -04:00
Alyssa Rosenzweig
5cf53d121c pan/bi: Streamline TEXC/TEXS naming/selection 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:14 -04:00
Alyssa Rosenzweig
6ed1bdfee4 pan/bi: Use canonical texture op names in IR 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:13 -04:00
Alyssa Rosenzweig
93f9052935 pan/bi: Fix simple txl test 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 731dfc6066 ("pan/bi: Allow vertex txl with lod=0 as compact")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:13 -04:00
Alyssa Rosenzweig
c3796c9f02 pan/bi: Expose GL 2.1 on Bifrost 
Needed for glamor. These features should work fine.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:13 -04:00
Alyssa Rosenzweig
a204eac759 pan/bi: Handle vector moves 
And fix the bad assertion that let this slip.

Like combines, nir_op_vec can be vector, and we need to lower this
ourselves. Thankfully, the lowering is simple.

Fixes
dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.nested_tricky_dataflow_1_*

Fixes: b2c6cf2b6d ("pan/bi: Eliminate writemasks in the IR")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:13 -04:00
Alyssa Rosenzweig
a22779866a pan/bi: Pass flow_control through directly 
More than just a single bool!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:12 -04:00
Alyssa Rosenzweig
0f181f4eae pan/bi: Use canonical flow control enum 
Merges multiple bits and adds some new combinations. The semantics are
the compiler are evidently wrong, we'll fix that next.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:12 -04:00
Alyssa Rosenzweig
d2328646b2 pan/bi: Use canonical term dependency 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:11 -04:00
Alyssa Rosenzweig
2b9484c2c8 pan/bi: Use canonical term "message type" 
These identify the type of message produced by a message-passing
instruction, rather than information about the clause per se.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:11 -04:00
Alyssa Rosenzweig
800ee3d303 pan/bi: Print message types as strings 
Even if we're not in verbose mode to match the canonical syntax.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:11 -04:00
Alyssa Rosenzweig
77a4e39100 pan/bi: Add missing message types 
Names are not canonical but that's ok.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:11 -04:00
Alyssa Rosenzweig
d2fac19999 pan/bi: Expand clause type to 5-bit 
The upper bit is reserved.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:10 -04:00
Alyssa Rosenzweig
785344e655 pan/bi: Use canonical name for staging registers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:10 -04:00
Alyssa Rosenzweig
4131bc3b0c pan/bi: Use canonical next_clause_prefetch 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:10 -04:00
Alyssa Rosenzweig
6c1cabc288 pan/bi: Canonicalize terminate_discarded_threads 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:09 -04:00
Alyssa Rosenzweig
a5975883b9 pan/bi: Use canonical floating-point modes 
First few pre-clause modifiers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:09 -04:00
Alyssa Rosenzweig
c8b9a05f9e pan/bi: Cull unnecessary edges on the CF graph 
If a block ends in an unconditional jump, we don't need to record a
fallthrough successor as well, since it's unreachable.

Likely harmless but makes the IR harder to parse with messy CF graphs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:09 -04:00
Alyssa Rosenzweig
026a29506e pan/bi: Drop if 0'd combine lowering 
This is supposed to be optimized but actually just broken. When we look
at optimizing this later we'll probably want a more straightforward copy
prop pass instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:08 -04:00
Alyssa Rosenzweig
405544eae5 pan/bi: Fix memory corruption in scheduler 
If empty the last will be bogus, I think. Missing Rust hard right around
now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:07 -04:00
Alyssa Rosenzweig
7c351a6f5d pan/decode: Ensure mappings are zeroed 
Fixes valgrind error when running with =sync

==30966== Conditional jump or move depends on uninitialised value(s)
==30966==    at 0x5B424E8: pandecode_find_mapped_gpu_mem_containing (decode_common.c:56)
==30966==    by 0x5B4CFB7: pandecode_jc (decode.c:2075)
==30966==    by 0x5ABBFA7: panfrost_batch_submit_ioctl (pan_job.c:1020)
==30966==    by 0x5ABD397: panfrost_batch_submit_jobs (pan_job.c:1042)
==30966==    by 0x5ABD397: panfrost_batch_submit (pan_job.c:1109)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:07 -04:00
Alyssa Rosenzweig
3ed7472b2a pan/bi: Add copy for register COMBINEs 
Fixes:

dEQP-GLES2.functional.shaders.loops.for_constant_iterations.infinite_with_conditional_break_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
 2020-10-10 16:53:06 -04:00
Christian Gmeiner
556bb17892 ci: piglit: conditionally build OpenCL tests 
For baremetal piglit this is not yet needed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7075>
 2020-10-10 11:56:03 +00:00
Jose Maria Casanova Crespo
d5e5f72e06 vc4: Enable lower_umax and lower_umin 
VC4 doesn't have support for UMAX and UMIN integer operations. So
we should avoid algebraic optimizations that generate umax/umin ops.

Fixes: 8e1b75b330 ("nir/algebraic: optimize iand/ior of (n)eq zero")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7083>
 2020-10-10 13:16:37 +02:00
Jose Maria Casanova Crespo
e7127b3468 nir/algebraic: optimize iand/ior of (n)eq zero when umax/umin not available 
Before 8e1b75b330 ("nir/algebraic: optimize iand/ior of (n)eq zero") this
optimization didn't need the use of umax/umin. VC4 HW supports only signed
integer max/min operations.

lower_umin and lower_umax are added to allow enabling previous optimizations
behaviour for this cases.

Fixes: 8e1b75b330 ("nir/algebraic: optimize iand/ior of (n)eq zero")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7083>
 2020-10-10 13:16:37 +02:00
Icecream95
210db65b1a panfrost: Add a debug flag to disable AFBC 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7076>
 2020-10-10 00:39:21 +00:00
Marek Olšák
205f1d79e2 radeonsi: disable SDMA on gfx6-7 and gfx10.3 to decrease CPU overhead 
same as gfx8-10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Marek Olšák
7a0162905b radeonsi: update the DMA perf test 
- don't test 2 waves/SA
- create the compute shader only once per subtest
- use only 1 TIME_ELAPSED query per subtest
- don't invalidate sL0 (it's not used)
- don't invalidate L2 for L2_LRU to test L2 throughput
- don't flush the CS after every run
- remove unused min/max computation

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Marek Olšák
4182fbcb60 winsys/amdgpu: apply the VM alignment optimization to the physical alignment too 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Marek Olšák
99446b8cee winsys/amdgpu: rework the VM alignment optimizations 
- don't increase the alignment past 2 MB
- apply the second tweak to older chips too

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Marek Olšák
a4e4644eff ac/surface: fix valgrind warnings in DCC retile tile lookups 
==12920== Conditional jump or move depends on uninitialised value(s)
==12920==    at 0x8F39391: util_fast_urem32 (fast_urem_by_const.h:71)
==12920==    by 0x8F39391: hash_table_search (hash_table.c:285)
==12920==    by 0x8B06D5D: ac_compute_dcc_retile_tile_indices (ac_surface.c:136)

Fixes: a37aeb128d "amd/common: Cache intra-tile addresses for retile map."

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Dave Airlie
b0df97b576 CI: build our own spirv tools 
This causes a lot of hiccups on the CL tests, but I've got most of
them fixed in another MR in pieces.

This should at least give a much more realistic baseline.

v2: use script in both places

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7073>
 2020-10-10 06:13:17 +10:00
Dave Airlie
d166188b84 ci: fix deqp clone + fetch 
This was taking > 10 minutes and I got bored, don't do a depth 1 fetch
in the first place just to do a proper fetch later.

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7073>
 2020-10-10 06:12:43 +10:00
John Bates
5de56937a3 disk_cache: build option for disabled-by-default 
On some systems it is problematic to have the shader cache enabled
by default. This adds a build option to support the disk cache but
keep it disabled unless the environment variable
MESA_GLSL_CACHE_DISABLE=false.

For example, on Chrome OS, Chrome already has it's own shader
disk cache implementation so it disables the mesa feature. Tests
do not want the shader disk cache enabled because it can cause
inconsistent performance results and the default 1GB for the
disk cache could lead to problems that require more effort to
work around. The Mesa shader disk cache is useful for VMs though,
where it is easy to configure the feature with environment
variables. With the current version of Mesa, Chrome OS would need
to have a system-wide environment variable to disable the disk
cache everywhere except where needed. More elegant to just build
Mesa with the cache feature disabled by default.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6967>
 2020-10-09 16:52:49 +00:00
Rhys Perry
8e981453ed radv: use radv_optimize_nir() less in radv_link_shaders() 
fossil-db (Navi):
Totals from 11 (0.01% of 137413) affected shaders:
CodeSize: 99372 -> 99480 (+0.11%)
Instrs: 19119 -> 19110 (-0.05%)
Cycles: 222144 -> 222000 (-0.06%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6891>
 2020-10-09 15:48:00 +00:00
Rhys Perry
55254f241f radv: move optimizations in shader_compile_to_nir() to after io_to_scalar 
This results in at least one less radv_optimize_nir() iteration.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6891>
 2020-10-09 15:47:59 +00:00
Rhys Perry
5f2671bcc5 nir: return progress from nir_lower_io_to_scalar_early 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6891>
 2020-10-09 15:47:59 +00:00
Boris Brezillon
fd4d0b447c panfrost: Move the blend shader cache at the context level 
Blend shaders can be shared among blend states, so let's move the blend
shader one level up so we don't have to re-create/re-compile shaders
when another blend state already asked for it.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
a5005c349d panfrost: Get rid of the constant patching done on blend shader binaries 
When constants are used in the blend equation we simply recompile the
shader.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
c9739941ba panfrost: Let compile_blend_shader() allocate the blend shader object 
This way we avoid an extra copy in panfrost_get_blend_shader().
Note that the allocation is attached to the blend state object
which simplifies the delete_blend_state() path.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
dbc33e8854 panfrost: Don't leak NIR blend shaders 
Right now we create shaders that are not attached to any memory
context, leading to memory leaks. Ideally, we should free the NIR
shader as soon as we've turned it into a binary, but there's no
function explicitly destroy a shader. Let's attach those to the blend
state so they get destroyed when this state is freed.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
8a5b885c94 panfrost: Allocate blit_blend with ralloc() 
This way we can use blend states as memory context which will help
simplify the blend shader creation/destruction logic.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
0a74a04ba5 panfrost: Pass compile arguments through a struct 
So we can extend it more easily without having to patch all callers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
78ec5225c2 panfrost: Move the blend constant mask extraction out of make_fixed_blend_mode() 
This way we can get a constant mask for the blend shader case too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Boris Brezillon
4441e80355 panfrost: Constify the rt_fmts arg passed to pan_lower_framebuffer() 
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
 2020-10-09 14:16:41 +00:00
Bas Nieuwenhuizen
da132d802b radv: Set fce metadata correctly on DCC initialization. 
The fce metadata can always be set to false as we don't care about
the compressed clear color.

Avoiding useless fast clear eliminates improves basemark performance by
1%-1.5%.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7005>
 2020-10-09 13:46:49 +00:00