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119 Commits

Author SHA1 Message Date
Marek Olšák
f7076d129d amd: add nir_intrinsic_xfb_counter_sub_amd and fix overflowed streamout offsets 
Fixes: 5ec79f9899 - ac/nir/ngg: nogs support streamout

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>
 2023-03-07 22:08:47 +00:00
Marek Olšák
9f1e6d8f70 nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd 
This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Caio Oliveira
e40b1df432 nir: Add nir_intrinsic_rotate 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19797>
 2023-02-24 06:33:51 +00:00
Georg Lehmann
ee47cc8256 amd,nir: remove byte_permute_amd intrinsic 
It's unused and if we ever want to use it again we should make it an alu
opcode instead.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21445>
 2023-02-22 20:13:52 +00:00
Daniel Schürmann
2bb369dd8d nir: add assertions that loops don't have a Continue Construct 
Hoping that I didn't miss any, this *should* add assertions
to all functions and passes which explicitly handle 'nir_loop'.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13962>
 2023-02-21 10:41:11 +00:00
Lionel Landwerlin
b82d9b1a3d nir/divergence: add missing RT intrinsinc handling 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20763>
 2023-01-18 22:32:43 +00:00
Lionel Landwerlin
3af08b9c30 nir/divergence: handle shader_record_ptr intrinsic 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes 6b8fd65e84 ("spirv: Implement the new ray-tracing storage classes")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20413>
 2022-12-23 09:22:13 +00:00
Qiang Yu
e85c5d8779 nir/divergence_analysis: add missing intrinsics 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
 2022-12-19 09:22:24 +08:00
Qiang Yu
1461b5f61b nir: add image fragment mask load intrinsic 
Like nir_texop_fragment_mask_fetch_amd, this is used to load multi
sample image fmask data for AMD GPU.

We will lower multi sample image load and samples_identical intrinsics
to use it latter for radeonsi. RADV does not need this because it
always expand fmask images before dispatch compute shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18666>
 2022-12-19 09:22:11 +08:00
Qiang Yu
796a150196 nir: add nir_load_ring_gs2vs_offset_amd 
Used by legacy GS output lowering.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20158>
 2022-12-13 11:42:33 +08:00
Qiang Yu
bb837bf6ef nir,ac/llvm: add nir_buffer_atomic_add_amd 
Used by radeonsi for lower nir_atomic_add_gen/xfb_prim_count_amd.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Qiang Yu
8030fbcf16 nir,ac/llvm: add nir_load_smem_buffer_amd 
Used by radeonsi to load const buffer.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
 2022-12-02 07:34:31 +00:00
Jason Ekstrand
4fb33124c3 nir/divergence: Handle base_workgroup_id and workgrpu_id_zero_base 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Lionel Landwerlin
99dcdf4d64 nir/divergence: add missing btd_shader_type_intel 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6d9ae6ec1e ("intel: add a new intrinsic to get the shader stage from bindless shaders")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19948>
 2022-11-23 15:04:22 +00:00
Qiang Yu
533b39bfcb nir,ac/llvm,radeonsi: add nir_load_clamp_vertex_color_amd 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19429>
 2022-11-11 04:22:20 +00:00
Rhys Perry
e6d26cb288 nir,ac/nir,aco,radv: replace has_input_*_amd with more general intrinsics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>
 2022-10-31 14:33:43 +00:00
Marek Olšák
0ac37b595a nir: add nir_intrinsic_optimization_barrier_vgpr_amd for LLVM 
We need this for the MSAA resolve shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>
 2022-10-29 18:38:33 +00:00
Qiang Yu
3d6cce2e4c nir: add two amd ngg lds base load intrinsics 
These two values are not known when compile for radeonsi.
They are relocated when link/upload time.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
 2022-10-27 07:35:01 +00:00
Lionel Landwerlin
117b32a594 nir/divergence_analysis: add missing desc_set_address_intel 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19320>
 2022-10-26 21:09:20 +00:00
Lionel Landwerlin
edda5731c0 nir/divergence_analysis: add some missing RT intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19320>
 2022-10-26 21:09:20 +00:00
Lionel Landwerlin
5a9f8d21d0 nir/lower_shader_calls: lower scratch access to format internally 
For a follow up optimization, we would like to track scratch loads.
This isn't possible with global load/store intrinsics. So use a couple
of special intrinsic in the pass and only lower it to global
intrinsics at the end.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16556>
 2022-10-26 12:53:25 +00:00
Rhys Perry
382831c986 radv,nir: add intrinsics for streamout and GS copy shaders 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19302>
 2022-10-25 17:35:08 +00:00
Qiang Yu
7fb506d068 nir: add nir_load_prim_xfb_query_enabled_amd 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17457>
 2022-10-25 12:58:43 +00:00
Qiang Yu
83643e4dc8 nir,ac/nir/ngg,radv: split shader_query_enabled_amd 
For used by different counter.

Vulkan:
1. VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT,
   sum generated primitives of all 4 streams when GS.
2. VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT, count generated
   primitives for all 4 streams when VS/TES/GS.
3. VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT, count generated
   and streamout primitives for all 4 streams when VS/TES/GS.

OpenGL:
1. GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB, sum generated
   primitives for all 4 streams when GS.
2. GL_PRIMITIVES_GENERATED, count generated primitives for all 4
   streams when VS/TES/GS.
3. GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN, count streamout
   primitives for all 4 streams when VS/TES/GS.

pipeline_stat_query_enabled_amd is for Vulkan 1 and OpenGL 1.
xfb_query_enabled_amd is for Vulkan 2/3 and OpenGL 2/3.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19015>
 2022-10-25 02:42:52 +00:00
Samuel Pitoiset
09033c7b22 nir: add nir_intrinsic_load_ring_attr_{offset}_amd 
These intrinsics will be used to lower NGG attributes to memory on
GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19173>
 2022-10-20 15:59:44 +00:00
Qiang Yu
58e006b174 nir,ac/llvm,radv: add nir_intrinsic_load_provoking_vtx_in_prim_amd 
For radeonsi which load this from arg.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19166>
 2022-10-20 06:53:56 +00:00
Samuel Pitoiset
dd30e7bfa0 nir: add nir_load_rasterization_samples_amd 
This will be used to load the number of rasterization samples when a
fragment shader is compiled inside a library without the MSAA state.
RADV needs to know the number of samples for loading sample positions
with interpolateAtSample().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
 2022-09-21 10:30:33 +00:00
Samuel Pitoiset
7f444fc72c nir: add nir_intrinsic_load_sample_positions_amd 
This will be used to lower barycentric_at_sample in NIR for RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
 2022-09-20 09:52:37 +00:00
Rhys Perry
7d26fafacf radv: fix dynamic RT stack size with VGPR spilling 
VGPR spilling might cause VGPRs to be spilled at scratch offset 0, so we
can't use that.

fossil-db (Sienna Cichlid, Q2RTX and Control):
Totals from 4 (0.26% of 1524) affected shaders:
Instrs: 8734 -> 8737 (+0.03%)
CodeSize: 48492 -> 48504 (+0.02%)
Latency: 384375 -> 384369 (-0.00%)
InvThroughput: 256250 -> 256246 (-0.00%)
Copies: 1312 -> 1313 (+0.08%)
Branches: 256 -> 258 (+0.78%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18541>
 2022-09-20 01:39:20 +00:00
Qiang Yu
4e06a8f15e nir: add nir_intrinsic_ordered_xfb_counter_add_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
1119e06a45 nir,ac/llvm: add nir_intrinsic_load_ordered_id_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
5c2d710064 nir: add nir_intrinsic_load_streamout_buffer_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
2ae357aa23 nir: add nir_intrinsic_load_num_vertices_per_primitive_amd 
This is used in streamout as radeonsi pass this value for VS
by arg.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
a19dcdf9d5 nir,ac/llvm: add nir_intrinsic_load_viewport_xy_scale_and_offset 
Used by RADV/Radeonsi NGG culling. Pack them into a single vec4
load for radeonsi to reduce const buffer load.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Qiang Yu
1aef9c8318 nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd 
Used by AMD GPU NGG line culling. We could use nir load
line width and viewport scale to calculate this in shader,
but this way needs expensive divide ops.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>
 2022-08-26 05:50:30 +00:00
Marek Olšák
6483fd394e nir: add nir_intrinsic_image_descriptor_amd 
This returns the AMD shader resource descriptor.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17693>
 2022-08-03 17:44:15 +00:00
Marek Olšák
ea6993f9c7 nir: add nir_intrinsic_image_samples_identical 
radeonsi will use it

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17693>
 2022-08-03 17:44:15 +00:00
Iago Toral Quiroga
b18cecbfb6 nir: add nir_address_format_2x32bit_global 
This adds support for global 64-bit GPU addresses as a pair of
32-bit values. This is useful for platforms with 32-bit GPUs
that want to support VK_KHR_buffer_device_address, which makes
GPU addresses explicitly 64-bit.

With the new format we also add new global intrinsics with 2x32
suffix that consume the new address format.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17275>
 2022-07-19 09:47:34 +02:00
Arvind Yadav
8adbd2a964 ac/llvm: Implement nir_intrinsic_load_point_coord_maybe_flipped opcodes 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15117>
 2022-07-16 07:08:10 -04:00
Qiang Yu
fdf589321c ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd 
Also add radv and radeonsi implementation. Will be used in tess lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
 2022-06-27 02:38:21 +00:00
Konstantin Seurer
16585664cd radv: vkCmdTraceRaysIndirect2KHR 
This changes the trace rays logic to always use
VkTraceRaysIndirectCommand2KHR and implements
vkCmdTraceRaysIndirect2KHR. I renamed the
load_sbt_amd to sbt_base_amd and moved the SBT
load lowering from ACO to NIR.

Note that we can not just upload one pointer to
all the trace parameters because that would
be incompatible with traceRaysIndirect.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
 2022-06-08 20:20:21 +00:00
Timur Kristóf
02c87e66e9 nir: Introduce new intrinsics for AMD specific mesh shader task ring. 
The mesh shader task ring is a buffer in VRAM which we will use to
store some mesh shader outputs that don't fit into LDS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
 2022-06-08 08:43:51 +00:00
Qiang Yu
33b4b923ee nir: add nir_intrinsic_load_lshs_vertex_stride_amd 
For loading LS-HS vertex stride by shader argument in radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
 2022-06-07 01:40:14 +00:00
Alyssa Rosenzweig
5c79d649af nir: Add transform feedback system values 
These will be used to facilitate transform feedback lowering for Panfrost,
although other backends could use the sysvals in the future.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15720>
 2022-06-04 14:35:56 +00:00
Lionel Landwerlin
5078b4fff1 nir/divergence: handle load_ray_num_dss_rt_stacks_intel 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16797>
 2022-06-01 04:58:50 +00:00
Lionel Landwerlin
d3c1b0ac28 nir/divergence: handle load_scratch_base_ptr 
v2: divergent (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16797>
 2022-06-01 04:58:50 +00:00
Marcin Ślusarz
b95d9bca1d nir: add load_task_payload intrinsic to nir_divergence_analysis 
It's divergent depending on sources.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16668>
 2022-05-24 17:53:29 +00:00
Marcin Ślusarz
95dbdbf063 nir: add load_mesh_inline_data_intel intrinsic to nir_divergence_analysis 
It's not divergent.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16668>
 2022-05-24 17:53:29 +00:00
Timur Kristóf
47da245ff2 nir: Add explicit task payload atomic intrinsics. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16693>
 2022-05-24 17:21:22 +00:00
Konstantin Seurer
938c9d9615 nir: Add a ray launch size addr intrinsic 
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15712>
 2022-05-12 15:04:31 +00:00