This is a full rewrite of the drawing and buffer management logic.
It offers a lot of improvements:
1. A copy of buffers is now always kept in system memory. This is
necessary to allow software processing of them, which is necessary
or improves performance in many cases.
2. Support for pushing vertices on the FIFO, with index lookup if necessary.
3. "Smart" draw code that tries to intelligently choose the cheapest
way to draw something: whether to use inline vertices or hardware
vertex buffer, and whether to use hardware index buffers
4. Support for all vertex formats supported by the hardware
5. Usage of translate to push vertices, supporting all formats that are
sensible to use as vertex formats
6. Support for base vertex
7. Usage of Ben Skeggs' primitive splitter originally for nv50, allowing
correct splitting of line loops, triangle fans, etc.
8. Support for instancing
9. Precomputation using the vertex elements CSO
Thanks to Ben Skeggs for his primitive splitter originally for nv50.
Thanks to Christoph Bumiller for his nv50 push code, that was the basis
of this work, even though I changed his code dramatically, in particular
to replace his ad-hoc vertex data emitter with translate.
The changes could also go into nv50 too, but there are substantial
differences due to the additional nv50 hardware features.
This is a significant refactoring of the sampling code that:
- Moves all generic functions in nvfx_fragtex.c
- Adds a driver-specific sampler view structure and uses it to
precompute texture setup as it should be done
- Unifies a bit more of code between nv30 and nv40
- Adds support for sampler view swizzles
- Support for specifying as sampler view format different from the
resource one (only trivially)
- Support for sampler view specification of first and last level
- Support for depth textures on nv30, both for reading depth and
for compare
- Support for sRGB textures
- Unifies the format table between nv30 and nv40
- Expands the format table to include essentially all supportable formats
except mixed sign and "autonormal" formats
- Fixes the "is format supported" logic, which was quite broken, and
makes it use the format table
Only tested on nv30 currently.
Seems a reasonable threshold for now.
Significantly speeds up Piglit's 1x1 glReadPixels (but, you know,
reading pixels in 1x1 blocks is NOT a good idea, especially if you
might be running on a less-than-perfect driver).
This patch adds support for creating temporary surfaces to allow
rendering to surfaces that cannot be rendered to.
It uses the _second_ version of the render temporary infrastructure.
This is necessary for swizzled 3D textures and small mipmaps of
swizzled 2D textures.
This version of the patch creates a resource to use as a temporary
instead of a raw BO, making the code simpler.
Now that the new 2D code is in place, swizzling can be safely enabled.
Render temporaries are needed in some cases, so this may degrade nv30
a bit until it gets render temporaries too.
This patch implements nv04_surface_copy/fill using the new 2D engine module.
It supports falling back to the 3D engine using the u_blitter module, which will be
added in a later patch.
Also adds support for using the 3D engine, reusing the u_blitter module
created for r300.
This is used for unswizzling and copies between swizzled surfaces.
This patch add a brand new nv04-nv40 2D engine module.
It should correctly implement all operations involving swizzled, and 3D-swizzled surfaces.
This code is independent from the Gallium framework and can thus be reused in the DDX and classic Mesa drivers (it's only likely to be useful in the latter, though).
Currently, surface_copy and surface_fill are broken for 3D textures, for swizzled source textures and possibly for some misaligned cases
The code is based around the new nv04_region structure, which encapsulates the information from pipe_surface needed for the 2D engine and CPU copies.
The use of nv04_region makes the code independent of the Gallium framework and allows to transform the nv04_region without clobbering the nv04_region.
The existing M2MF, blitter, and SWIZZLED_SURFACE paths have been improved and a new CPU path has been added.
There is also support to tell the caller to use the 3D engine.
The main feature of the copy/fill setup algorithm is linearization/contiguous-linearization of swizzled surfaces.
The idea of linearization is that some swizzled surfaces are laid out like linear ones (1xN, 2xN, Nx1) and can thus be used as such (e.g. useful for copying single pixels).
Also, some rectangles (e.g. the whole surface) are contiguous in memory. If both the source and destination rectangles are swizzled but contiguous, then they can be regarded as both linear: this is the idea of "contiguous linearization".
This, for instance, allows to use the 2D engine to duplicate the content of a swizzled surface to another swizzled surface, by pretending they are actually linear.
After linearization, the result may not be 64-byte aligned. Another transformation is done to enlarge the linear surface so that it becomes 64-byte aligned.
This is also used to 64-byte align swizzled texture mipmaps.
The inner loop of the CPU path is as optimized as possible without using SSE/SSE2.
Future improvements could include SSE/SSE2 support, and possibly a faster coordinate swizzling algorithm (which is however not used in the inner loop).
It may be a good idea to autogenerate swizzling code at least for all possible POT 2D texture dimensions (less than 256), maybe for all 3D ones too (less than 4096).
Also, it woud be a very good idea to make a copy with the GPU first if the source surface is in uncached memory.
This greatly simplifies the code, and avoids ad-hoc copy code.
Also, these new transfers work for buffers too, even though they
are still used for miptrees only.
Changes:
- Disable swizzling on non-RGBA 2D textures, since the current 2D
code is mostly broken in those cases. A later patch will fix this.
Thanks to Andrew Randrianasulu who reported this.
- Fix compressed texture transfers and hack around the current 2D
code inability to copy compressed textures by using direct access.
Thanks to Andrew Randrianasulu who reported this.
This patch rewrites all the miptree layout and transfer code in the
nvfx driver.
The current code is broken in several ways:
1. 3D textures are laid out first by face, then by level, which is
incorrect
2. Cube maps should have 128-byte aligned faces
3. Swizzled textures have a strange alignment test that seems
unnecessary
4. We store the image_offsets for each face/slice but they can be
easily computed instead
5. "Swizzling" is not supported for compressed formats. They can be
"swizzled" but swizzling only means that there are no gaps (pitch is
level-dependant) and the layout is still linear
6. Swizzling is not supported for non-RGBA formats. All formats (except
possibly depth) can be swizzled according to my testing.
The miptree layout is rewritten based on my empirical testing, which I
posted in the "miptree findings" mail.
The image_offset array is removed, since it can be calculated with a
simple multiplication; the only array in the miptree structure is now
the one for mipmap level starts, which it seems cannot be easily
computed in constant time.
Also, we now directly store a nouveau_bo instead of a pipe_buffer in
the miptree structure, like nv50 does.
Support for render temporaries is removed, and will be readded in a
later patch.
Note that the current temporary code is broken, because it does not
copy the temporary back on render cache flushes.
The trace driver's implementation of sampler_view_destroy was calling
directly into the underlying pipe's sampler_view_destroy implementation.
This causes problems for pipes that keep references to sampler views
even after the state tracker has released them. Instead, we'll simply
drop the trace driver's reference to the pipe's sampler view.
Signed-off-by: José Fonseca <jfonseca@vmware.com>
The trace driver was tracing the unwrapped version of the index buffer
when setting the index buffer. This caused an assert validating that
a resource belonged to the trace driver to fail. Instead, we'll log
the unmodified index buffer structure when setting the index buffer.
Signed-off-by: José Fonseca <jfonseca@vmware.com>
