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Author SHA1 Message Date
Jesse Natalie
f59e6ad5d7 CI: Use a sha for the Windows SPIRV-LLVM-Translator dependency 
Acked-by: Daniel Stone (daniels@collabora.com)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9018>
 2021-02-16 18:33:18 +00:00
Mike Blumenkrantz
d451285e45 zink: fix device codegen extension detection 
the logic for this was broken and failed to detect any extensions other
than the first one listed. instead, we must follow this logic chain:
1. check the extension name
  2a. if this is an extension that got promoted to core, check the @since version
    3a. if current version >= @since version
      4a. if the extension has required features/properties, check those
      4b. else set supported
    3b. else
      4a. if the extension has required features/properties, check those
      4b. else set supported
  2b. else
    4a. if the extension has required features/properties, check those
    4b. else set supported

Fixes: efe6f00e34 ("zink/codegen: do not enable extensions that are now core")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9081>
 2021-02-16 18:23:31 +00:00
Jason Ekstrand
2491d5a662 nir/algebraic: Covert up-cast of down-cast to extract on Intel 
This starts generating extract for bit sizes other than 32 but our
back-end handles that just fine.

Reviewed-by: Ian Romanick <ian.d.romanick@.intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Jason Ekstrand
f9b3be09e1 nir/algebraic: Clean up up-cast of down-cast when we can 
There are a bunch of cases where we can pretty quickly determine that
the high bits don't matter.  In these cases, delete the casts.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Jason Ekstrand
96303a59ea nir: Add some range analysis for used bits 
This isn't 100% accurate, of course, but it should be good enough for
what we're about to do with it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Jason Ekstrand
d670afa27a intel/nir: Lower 8-bit phis on Gen11+ 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Jason Ekstrand
d41ac6e2ca nir/lower_bit_size: Support phi instructions 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Jason Ekstrand
6413e67591 nir: Add a couple helpers for phis and cursors 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8872>
 2021-02-16 16:36:31 +00:00
Rohan Garg
6dfdde149e virgl: Return total video memory if available 
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9009>
 2021-02-16 16:09:15 +00:00
Rohan Garg
e778aceaae virgl: update headers 
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9009>
 2021-02-16 16:09:14 +00:00
Thong Thai
38f012e023 frontends/va/config: Fix check for packed header config 
Fixes: b4651890be ("frontends/va: Update conditional checks for code stability.")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4285
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9020>
 2021-02-16 15:29:39 +00:00
Gustavo Padovan
74f9bcc21c gitlab-ci: add intel APL and GLK devices with manual triggers 
This add support for the Intel Apollo Lake and Gemini Lake families,
however the job will be disabled by default unless the developer
manually hit play for the iris-apl-traces and iris-glk-traces jobs in
GitLab CI.

These devices are still under experimental level support in
the Lava lab and are not guaranteed to work reliably yet. Once they
become reliable and more resilient we will enable them by default in
MesaCI.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
 2021-02-16 15:08:27 +01:00
Gustavo Padovan
6ec815cfd2 gitlab-ci: build the iris gallium driver as well 
For now we will start with iris. Our main focus is to enable the devices
to be used in MesaCI.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
 2021-02-16 15:08:27 +01:00
Gustavo Padovan
e2b5def1f0 gitlab-ci: extend x86_64 kernel config to suport Intel devices 
There are extra kernel config options we need to enable for Intel.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
 2021-02-16 15:08:26 +01:00
Rohan Garg
56bbbc8322 intel/compiler: Free resources on test teardown 
Ensure that all resources are properly released by
properly parenting them to a memory context and releasing
the context during test teardown.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
 2021-02-16 15:07:52 +01:00
Rohan Garg
628c10f14e intel/genxml: Free resource before exiting 
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8162>
 2021-02-16 15:07:52 +01:00
Icecream95
9bb376bbdb pan/bi: Use the correct size for UBO loads 
Multiply by the destination bit size to get the number of bits to
load instead of assuming 32 bits.

Fixes: 2e57684d2d ("pan/bi: Implement load_ubo with the builder")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9071>
 2021-02-16 13:14:30 +00:00
Bas Nieuwenhuizen
596fb88c01 radv: Do pipe misalignment check per plane. 
Fixes: 4c99d6ff54 ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9078>
 2021-02-16 13:04:09 +00:00
Arcady Goldmints-Orlov
7f61ff7b4d broadcom/compiler: Merge instructions more efficiently 
Instructions are allowed to access up to two rf registers, or one rf
register and a small immediate. This change allows qpu_merge_inst to
take full advantage of this by allowint the merging of two instructions
if they have no more than two different rf registers between them,
or one rf register and one small immediate. qpu_merge_inst rewrites
the instructions as needed to pack everything into raddr_a and raddr_b
in the merged instruction.

shader-db stats:
total instructions in shared programs: 19938769 -> 18929664 (-5.06%)
instructions in affected programs: 17929438 -> 16920333 (-5.63%)
helped: 95008
HURT: 242
helped stats (abs) min: 1 max: 785 x̄: 10.62 x̃: 7
helped stats (rel) min: 0.30% max: 21.25% x̄: 5.37% x̃: 4.98%
HURT stats (abs)   min: 1 max: 2 x̄: 1.10 x̃: 1
HURT stats (rel)   min: 0.30% max: 3.12% x̄: 1.62% x̃: 1.54%
95% mean confidence interval for instructions value: -10.67 -10.52
95% mean confidence interval for instructions %-change: -5.37% -5.33%
Instructions are helped.

total max-temps in shared programs: 3122664 -> 3112446 (-0.33%)
max-temps in affected programs: 124881 -> 114663 (-8.18%)
helped: 5445
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.88 x̃: 1
helped stats (rel) min: 1.49% max: 40.54% x̄: 8.97% x̃: 6.67%
95% mean confidence interval for max-temps value: -1.91 -1.84
95% mean confidence interval for max-temps %-change: -9.12% -8.81%
Max-temps are helped.

total sfu-stalls in shared programs: 38028 -> 41231 (8.42%)
sfu-stalls in affected programs: 6053 -> 9256 (52.92%)
helped: 664
HURT: 3380
helped stats (abs) min: 1 max: 2 x̄: 1.04 x̃: 1
helped stats (rel) min: 9.09% max: 100.00% x̄: 70.81% x̃: 100.00%
HURT stats (abs)   min: 1 max: 4 x̄: 1.15 x̃: 1
HURT stats (rel)   min: 0.00% max: 300.00% x̄: 46.39% x̃: 25.00%
95% mean confidence interval for sfu-stalls value: 0.76 0.82
95% mean confidence interval for sfu-stalls %-change: 25.03% 29.26%
Sfu-stalls are HURT.

total inst-and-stalls in shared programs: 19976797 -> 18970895 (-5.04%)
inst-and-stalls in affected programs: 17963129 -> 16957227 (-5.60%)
helped: 95017
HURT: 245
helped stats (abs) min: 1 max: 785 x̄: 10.59 x̃: 7
helped stats (rel) min: 0.30% max: 21.25% x̄: 5.35% x̃: 4.95%
HURT stats (abs)   min: 1 max: 2 x̄: 1.09 x̃: 1
HURT stats (rel)   min: 0.30% max: 3.12% x̄: 1.61% x̃: 1.54%
95% mean confidence interval for inst-and-stalls value: -10.64 -10.48
95% mean confidence interval for inst-and-stalls %-change: -5.35% -5.31%
Inst-and-stalls are helped.

v2 (Iago):
 - moved early return for naddrs > 2 even earlier.
 - only update {add,mul}.b mux if instruction has more than one operand.
 - don't OR b->raddr_{a,b} if we are not merging add/mul instructions.
 - don't initialize packed to 0.
 - minor style fixes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9026>
 2021-02-16 11:46:31 +00:00
Michel Zou
6ccbb89207 meson: invalid keyword argument dependencies 
Fixes: e4cc52c0 (vulkan: Add common extension tables)
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8821>
 2021-02-16 11:35:32 +00:00
Samuel Pitoiset
f502bdf1ab radv: only apply the MRT output NaN fixup to non-meta shaders 
We only want this workaround to be applied for game shaders.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4163
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9048>
 2021-02-16 09:03:31 +01:00
Christian Gmeiner
309f9f565f ci: Update baremetal kernel to 5.11 plus patches 
For imx6 we need the following fec ethernet fix:
 c730ab423bfa ("net: fec: Fix temporary RMII clock reset on link up")

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9046>
 2021-02-16 06:56:24 +00:00
Dave Airlie
98b6cd157a lavapipe: add support for missing 10/10/10/2 formats. 
The snorm formats don't work for blitting, so don't expose
them for that.

This passes all CTS tests that it enables.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8907>
 2021-02-16 05:31:11 +00:00
Dave Airlie
1797e4ebc5 lavapipe: add support for 2/10/10/10 scaled formats. 
These will be used for zink CI testing.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8907>
 2021-02-16 05:31:11 +00:00
Dave Airlie
4326c5460d llvmpipe: don't support scaled formats outside vertex buffers 
Scaled formats are usually only needed as vertex buffer formats,
don't expose them as supported for other things.

Lavapipe will use this to export the correct formats support.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8907>
 2021-02-16 05:31:11 +00:00
Dave Airlie
8258726d90 util/format: add helper to check if a format is scaled. 
lavapipe/llvmpipe need this to rule out scaled formats for non-vertex
format usage. Note NONE is defined as scaled in u_format, but for
the purposes of this helper I don't want it to be considered scaled.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8907>
 2021-02-16 05:31:11 +00:00
Mike Blumenkrantz
2b6d59bd8c zink: support nir_intrinsic_group_memory_barrier 
needed for cts

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9073>
 2021-02-15 22:38:06 -05:00
Mike Blumenkrantz
a14610281a features: mark off GL 4.6 and ES 3.1 for zink 
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:30 +00:00
Mike Blumenkrantz
0960938d86 zink: GLSL 460 
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:30 +00:00
Mike Blumenkrantz
efc219f1c4 zink: PIPE_CAP_GL_SPIRV 
still needs a bunch of fixing, but 75% of tests pass

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
cb5957e13d zink: enable pipeline statistics cap 
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
5a4f5d1bb5 zink: enable PIPE_CAP_QUERY_SO_OVERFLOW 
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
3d7d55c2cf zink: enable PIPE_CAP_POLYGON_OFFSET_CLAMP 
this is already handled

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
670b79ffd5 zink: enable PIPE_CAP_DRAW_PARAMETERS 
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
75baabf9fb zink: enable PIPE_CAP_TGSI_VOTE 
ARB_shader_group_vote

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9072>
 2021-02-16 01:16:29 +00:00
Mike Blumenkrantz
759a71b67d zink: add util function for submitting the compute batch 
sometimes we just want to submit this and not wait on it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9063>
 2021-02-16 01:05:07 +00:00
Mike Blumenkrantz
f1bc95bfa5 zink: rewrite drawid based on shader key value 
same as basevertex

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
7fad9d647a zink: break out push constant creation in compiler and add drawid value 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
a0911f825d zink: add a vs shader key for rewriting gl_DrawID 
if we get a direct draw, we have to rewrite the drawid for it to work as expected

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
165a940fc2 zink: add a draw_id param to vs push constants 
gallium always gives us multidraws as individual draws, so we need to feed
this through to the shader

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
55abc1202c zink: wrap shader gl_BaseVertex access with a bcsel based on push constant state 
vulkan has different mechanics than gl for this variable based on whether the
current draw is indexed, so we need to rewrite the access here for that case

this also requires that we add some padding to the tcs shader injection to
account for new members being added to the push constant

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
bf4fac51ee zink: add push constant value to indicate whether the current draw is indexed 
due to semantic differences between gl and vk variables, this is going to be
necessary for gl_BaseVertex

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
59aae6db9f zink: rework tcs injection to be more compatible with new push const struct 
we can simplify the push constant loader to directly take the struct member
index here and then pass that directly to simplify things for future use

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
00642ab6ed zink: create a struct for tracking push constant layout 
it'll be helpful to update this as we add more values here so we can
avoid having to update all the users

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
c28bc38f94 zink: add handling for ARB_shader_draw_parameters variables in ntv 
* gl_DrawID
* gl_BaseVertex
* gl_BaseInstance (was already semi-handled)

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8971>
 2021-02-16 00:52:32 +00:00
Mike Blumenkrantz
8300bc1f16 zink: handle 1bit undef values in ntv 
spirv requires that 1bit values be bool types, not uints

Fixes: 93af00502e ("zink: use uvec for undefs")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9059>
 2021-02-15 21:17:07 +00:00
Mike Blumenkrantz
e3428419fb zink: fix slot mapping for legacy gl io with tess stages 
e.g., gl_BackColor is a thing

Fixes: aec03553e1 ("zink: fix tess shader i/o variables")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9019>
 2021-02-15 20:47:14 +00:00
Mike Blumenkrantz
2b6950c3fd zink: add support for pipeline statistics queries 
so easy!

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9010>
 2021-02-15 20:37:22 +00:00
Mike Blumenkrantz
ff0233353a zink: hook up cs invocation queries to the compute batch 
compute batches are separate, so we have to run these queries on the
appropriate batch to see the expected results

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9010>
 2021-02-15 20:37:22 +00:00
Mike Blumenkrantz
942ba4e341 zink: unset generated TCS if its parent TESS is unset 
ensure this doesn't get pulled in during the next program update

Fixes: 334759d850 ("zink: implement passthrough tcs shader injection")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9057>
 2021-02-15 20:03:23 +00:00