Commit Graph

189850 Commits

Author SHA1 Message Date
Marek Olšák
f493d6fb6f radeonsi: don't lower UBO/SSBOs to descriptors if they are already lowered
The next change will depend on this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
e1c65ce680 radeonsi/gfx12: fix a regression in si_init_depth_surface
si_htile_enabled has an assertion not expecting GFX12

Fixes: d0810d528c - radeonsi: use the common helper for initializing DS surfaces

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
321cb43c11 radeonsi/gfx12: fix depth bounds register values
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
59d7d06828 radeonsi/gfx12: fix a regression in si_set_mutable_tex_desc_fields
Fixes: 26cd3a1718 - ac,radv,radeonsi: add a helper to set mutable tex desc fields

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
a548ec7ad4 radeonsi/gfx12: disable CU1 instead of CU0 for GS due to SQTT
SQTT captures traces from CU0, so we need to keep it enabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
34be14d957 radeonsi/gfx12: fix incorrect condition for when to do clear_buffer via compute
It was missing the requirement that offset % 4 == 0.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
76b0ad33bc radeonsi/gfx12: fix the alpha ref value
This was missed when the code was refactored.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
3ab0e18db4 radeonsi: vectorize loads/store after ABI lowering and optimizations
This results in slightly better code.

  SGPRs: 3552 -> 3608 (1.58 %)
  VGPRs: 1988 -> 2020 (1.61 %)
  Code Size: 178036 -> 177664 (-0.21 %) bytes
  Max Waves: 1136 -> 1136 (0.00 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
35c5435eae ac/llvm: fix incorrect parameter type in llvm.amdgcn.s.nop
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
ad07ea3162 amd: enable 32B minimum DCC block size for gfx1151
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
cf4eb41540 amd: add more gfx11 APUs
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Marek Olšák
7650127040 amd: update addrlib
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29313>
2024-05-24 13:48:28 +00:00
Natanael Copa
0274518615 nir/opt_varyings: reduce stack usage
Avoid put a huge struct on stack to fix a stack overflow on musl libc.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10988
Fixes: c66967b5cb (nir: add nir_opt_varyings, new pass optimizing and compacting varyings)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29375>
2024-05-24 13:15:33 +00:00
Valentine Burley
f7a262cd6d freedreno/devices: Fix indentation for Adreno A32
Adjust indentation to match other entries.

Fixes: cd7da3a807 ("freedreno/devices: Add support for Adreno A32 (G3x Gen 2)")
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29347>
2024-05-24 12:21:07 +00:00
Valentine Burley
674d5b54bf tu: Expose VK_EXT_nested_command_buffer
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29347>
2024-05-24 12:21:07 +00:00
Samuel Pitoiset
cd5f980d51 ac,radv,radeonsi: move ZRANGE_PRECISION to mutable DS fields
The DS surfaces are now completely configured in common code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
2024-05-24 11:48:32 +00:00
Samuel Pitoiset
332a06903d ac,radv,radeonsi: a function that sets mutable DS surface fields
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
2024-05-24 11:48:32 +00:00
Samuel Pitoiset
1a08fa6150 ac,radv,radeonsi: add function to get the number of ZPLANES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
2024-05-24 11:48:32 +00:00
Samuel Pitoiset
709452b9d1 radv: do not check image usage for ITERATE256 with TC-compat HTILE
This is redundant because TC-compat HTILE is only enabled for images
that are readable by shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
2024-05-24 11:48:32 +00:00
Samuel Pitoiset
dcfa351af3 radv: only enable DB_STENCIL_INFO.ITERATE_FLUSH when necessary
When no HTILE for stencil this shouldn't be neessary.
This also matches RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29349>
2024-05-24 11:48:32 +00:00
Constantine Shablia
2adf01fa61 panvk: enable KHR and EXT BDA
And get it tested by CI.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29302>
2024-05-24 13:07:26 +02:00
Boris Brezillon
deb9756e23 panvk: Lower global memory IOs
If we want to support KHR_buffer_device_address, we need to lower global
IOs.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29302>
2024-05-24 13:06:50 +02:00
Mary Guillemard
fe59b772b5 bi: Alloc replacement array once in opt_cse
This create an uneeded pressure otherwise.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29372>
2024-05-24 11:16:31 +02:00
Mary Guillemard
01ea55b44c midgard: Reformat code
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29372>
2024-05-24 11:16:31 +02:00
Mary Guillemard
547308990d bi: Reformat code
Had some broken formatting.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29372>
2024-05-24 11:16:03 +02:00
Lionel Landwerlin
2c65d90bc8 intel/brw: ensure find_live_channel don't access arch register without sync
Another architecture register that requires some care before reading.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 49ee3ae9e8 ("intel/compiler: Lower FIND_[LAST_]LIVE_CHANNEL in IR on Gfx8+")
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29319>
2024-05-24 07:26:17 +00:00
Eric Engestrom
1add55863f zink+nvk/ci: spec@ext_external_objects@vk-vert-buf-reuse has been fixed
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29371>
2024-05-24 08:48:07 +02:00
Eric Engestrom
ace5c27898 zink+nvk/ci: add more flakes seen in nightly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29371>
2024-05-24 08:47:20 +02:00
Eric Engestrom
6789d4c0b2 zink+nvk/ci: more KHR-GL46.packed_pixels.varied_rectangle.* flakes, so mark the group as flaky
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29371>
2024-05-24 08:45:39 +02:00
Eric Engestrom
6843a7951b ci/b2c: make B2C_JOB_WARN_REGEX optional
Fixes: bfd4db0476 ("radv/ci: move amdgpu-specific kernel message warning to src/amd/ci/")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29368>
2024-05-24 05:58:26 +00:00
Iago Toral Quiroga
865e682ad7 broadcom/compiler: apply payload conflict to spill setup before RA
We can emit spill setup before RA if we use scratch. In that case
we have the same situation as during spilling, with the caveat that
we have already emitted the instructions so we need to find them
(they should be the only instructions ones before the instructions
accessing payload registers) and flag them as such.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29343>
2024-05-24 05:25:22 +00:00
Iago Toral Quiroga
cb83f25b39 broadcom/compiler: don't assign payload registers to spilling setup temps
We read our payload registers first in the shader so we generally don't have
to care about temps being allocated to them and stomping their value before
we can read them. Hoewer, spilling setup instructions are an exception since
these will be inserted first when there is any spilling in the program.
To fix this, we flag RA nodes involved with these instructions so we can
then try to avoid assiging these registers to them.

Fixes CTS failures with V3D_DEBUG=opt_compile_time, particularly:
dEQP-VK.binding_model.buffer_device_address.set0.depth2.basessbo.convertcheckuv2.nostore.single.std140.comp_offset_nonzero

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29343>
2024-05-24 05:25:22 +00:00
Iago Toral Quiroga
901c485997 broadcom/compiler: make add_node return the node index
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29343>
2024-05-24 05:25:21 +00:00
David Heidelberg
33492dd9e8 ci/radv: dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units passes now
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29367>
2024-05-24 03:45:44 +00:00
David Heidelberg
c39cf7bcab docs: correct svga3d redirected URLs
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29366>
2024-05-24 03:19:21 +00:00
David Heidelberg
fca045f02f ci/freedreno: a3xx will never have Vulkan support
Do not spam CI logs.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29365>
2024-05-24 02:56:47 +00:00
Yiwei Zhang
c71f650c2d ci/venus: skip a timeout test
There're already a few similar ones being skipped.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29362>
2024-05-24 02:34:45 +00:00
Yiwei Zhang
60488962db venus: allow non-wsi image alias path to passthrough upon bind memory
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29362>
2024-05-24 02:34:45 +00:00
Yiwei Zhang
c97f9193ef venus: drop internal memory pools
This exists due to historical limitations which have long gone obsolete.
This persists longer due to hostorical perf issues that have recently
gone obsolete on the platforms shipping Venus. Meanwhile, clients like
skiavk and ANGLE nowadays do a better job managing suballocations. The
tiny perf win from having this giant internal pool has been beaten by
the memory waste, longer one-shot jank due to largier alloc, allocations
no need to be mapped but only because host-visible is advertised across
mem types and varies workarounds and markups needed to make alignment
work and make VVL happy. Dropping it also reduces the maintenance cost.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29362>
2024-05-24 02:34:45 +00:00
David Heidelberg
db62ec3370 ci/nouveau: adjust and add DEVICE_TYPE
Rather than string made from farm-device, use DTB as we use for most of
the DEVICE_TYPE entries.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26758>
2024-05-23 22:50:20 +00:00
David Heidelberg
18eb91da59 ci/nouveau: separate HW definition from SW
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26758>
2024-05-23 22:50:20 +00:00
David Heidelberg
6bc660a542 ci/nouveau: move disabled jobs back from include into main gitlab-ci.yml
Fixes: 9442571664 ("ci: separate hiden jobs to -inc.yml files")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26758>
2024-05-23 22:50:20 +00:00
David Heidelberg
d315585d89 ci/r300: update flake list from nightly reports
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29255>
2024-05-23 21:32:35 +00:00
Rob Clark
450c9460c6 freedreno/loader: Switch over to probe_nctx
Unwind the hacks that were previously used for freedreno to probe on
virtgpu, and switch over to the new mechanism.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28777>
2024-05-23 20:02:04 +00:00
Rob Clark
2ea4a59ab7 loader: Add better support for virtgpu nctx driver loading
In the case of virtio_gpu, if the drm native context capset is
supported, we should try loading the native driver before falling back
to virgl.

Previously this was done with hacks in pipe_virtio_gpu_create_screen(),
but this also requires virgl's driconf to be the superset of virgl and
all the nctx drivers.

Instead add an optional loader callback to probe for nctx support.  This
is called with the drm capset, if the host supports the drm context
type, to allow driver specific code to determine if the specific GPU is
supported, so we can cleanly fall back to virgl if it does not (for ex,
an old VM guest with a newer host, where mesa in the guest does not
support the new GPU, but mesa in the host does).

TODO: How to handle the dynamic loader case?

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28777>
2024-05-23 20:02:03 +00:00
Rob Clark
27ebf58ee8 virgl: Update headers
VIRGL_RENDERER_UNSTABLE_APIS has been dropped upstream

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28777>
2024-05-23 20:02:03 +00:00
Rob Clark
bba6418fcb freedreno: Namespace DEFINE_CAST()
Otherwise it conflicts with a similar macro in drm_hw.h.  (Which should
also be renamed, but better to rename that in virglrenderer tree first.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28777>
2024-05-23 20:02:03 +00:00
Lionel Landwerlin
5f2288095b anv: fix shader identifier handling
When compilation is required, we should return
VK_PIPELINE_COMPILE_REQUIRED. The spec prevents the application from
passing a module or SPIR-V code so we have nothing to compile if the
cache lookup fails :

VUID-VkPipelineShaderStageCreateInfo-stage-06844:
   If a shader module identifier is specified for this stage, a
   VkShaderModuleCreateInfo structure must not be present in the pNext
   chain

VUID-VkPipelineShaderStageCreateInfo-stage-06848:
   If a shader module identifier is specified for this stage, module
   must be VK_NULL_HANDLE

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11208
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29340>
2024-05-23 19:05:05 +00:00
Eric Engestrom
bfd4db0476 radv/ci: move amdgpu-specific kernel message warning to src/amd/ci/
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29339>
2024-05-23 18:28:41 +00:00
Caio Oliveira
e3099fc839 spirv: Add MESA_SPIRV_DEBUG=values to dump all values
Dumps the value associated with each SPIR-V ID after parsing the module.
This will show the intermediate vtn_* values that spirv_to_nir uses.
Only a subset of detailed information is printed at the moment (focus on
pointers and pointer types), but it is easy to add for other value types
later.

Example output when running crucible with the debug option enabled.

```
    crucible: start  : func.compute.num-workgroups.basic.q0
    === SPIR-V values
           1 = extension
           2 = type void glsl_type=void
           3 = type function
           4 = function
           5 = block
           6 = type scalar glsl_type=uint
           7 = type vector glsl_type=uvec3
           8 = type array glsl_type=uvec3[]
           9 = type struct glsl_type=Storage
          10 = type pointer deref=9 SpvStorageClassUniform glsl_type=uvec4
          11 = pointer ptr_type=10 (pointed-)type=9
          12 = type scalar glsl_type=int
          13 = constant type=12
          14 = type pointer deref=7 SpvStorageClassInput glsl_type=uint
          15 = pointer ptr_type=14 (pointed-)type=7
          16 = constant type=6
          17 = type pointer deref=6 SpvStorageClassInput glsl_type=uint
          18 = pointer ptr_type=17 (pointed-)type=6
               NIR: 32    %2 = deref_array &(*%0)[0] (system uint)  // &gl_LocalInvocationID[0]
          19 = ssa glsl_type=uint
          20 = pointer ptr_type=14 (pointed-)type=7
          21 = ssa glsl_type=uvec3
          22 = type pointer deref=7 SpvStorageClassUniform glsl_type=uint
          23 = pointer ptr_type=22 (pointed-)type=7
               NIR: 32x4  %12 = deref_array &(*%11)[%4] (ssbo uvec3)  // &((Storage *)%9)->uv3a[%4]
          24 = constant type=6
          25 = constant type=6
          26 = constant type=7
    ===
    crucible: pass   : func.compute.num-workgroups.basic.q0
```

When the environment variable is set, this dump will also be printed
during vtn_fail and its helpers.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29295>
2024-05-23 17:07:31 +00:00